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Sat, 15 Sep 2018 07:30:40 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1g1Bal-0004sf-Kx; Sat, 15 Sep 2018 07:30:35 -0700 Received: from xsj-pvapsmtp01 (smtp2.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id w8FEUOGS031555; Sat, 15 Sep 2018 07:30:24 -0700 Received: from [172.23.64.8] (helo=xhdvnc108.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1g1BaZ-0004qJ-Vc; Sat, 15 Sep 2018 07:30:24 -0700 Received: by xhdvnc108.xilinx.com (Postfix, from userid 15427) id 9C1F9604AD; Sat, 15 Sep 2018 20:00:23 +0530 (IST) From: Anurag Kumar Vulisha To: , CC: , , , , , Anurag Kumar Vulisha Subject: [PATCH v5 7/8] usb: dwc3: Check for IOC/LST bit in both event->status and TRB->ctrl fields Date: Sat, 15 Sep 2018 20:00:00 +0530 Message-ID: <1537021801-23896-8-git-send-email-anurag.kumar.vulisha@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1537021801-23896-1-git-send-email-anurag.kumar.vulisha@xilinx.com> References: <1537021801-23896-1-git-send-email-anurag.kumar.vulisha@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(376002)(346002)(39860400002)(396003)(136003)(2980300002)(438002)(199004)(189003)(6666003)(81156014)(47776003)(305945005)(5660300001)(42186006)(106002)(336012)(16586007)(316002)(51416003)(356003)(8936002)(4326008)(103686004)(106466001)(81166006)(126002)(2616005)(110136005)(39060400002)(50226002)(54906003)(11346002)(8676002)(426003)(6266002)(446003)(76176011)(486006)(476003)(63266004)(107886003)(478600001)(186003)(48376002)(50466002)(36756003)(14444005)(36386004)(26005)(90966002)(2906002)(52956003)(107986001);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR02MB5120;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;A:1;MX:1; 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This logic doesn't work if multiple TRBs are queued per request and the IOC/LST bit is set on the last TRB of that request. Consider an example where a queued request has multiple queued TRBs and IOC/LST bit is set only for the last TRB. In this case, the Core generates XferComplete/XferInProgress events only for the last TRB (since IOC/LST are set only for the last TRB). As per the logic in dwc3_gadget_ep_reclaim_completed_trb() event->status is checked for IOC/LST bit and returns on the first TRB. This makes the remaining TRBs left unhandled. To aviod this, changed the code to check for IOC/LST bits in both event->status & TRB->ctrl. This patch does the same. Signed-off-by: Anurag Kumar Vulisha Reviewed-by: Thinh Nguyen --- Changes in v5: 1. None Changes in v4: 1. None Changes in v3: 1. None Changes in v2: 1. None --- drivers/usb/dwc3/gadget.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 1cb7df9..872c956 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -2299,7 +2299,12 @@ static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep, if (event->status & DEPEVT_STATUS_SHORT && !chain) return 1; - if (event->status & (DEPEVT_STATUS_IOC | DEPEVT_STATUS_LST)) + if ((event->status & DEPEVT_STATUS_IOC) && + (trb->ctrl & DWC3_TRB_CTRL_IOC)) + return 1; + + if ((event->status & DEPEVT_STATUS_LST) && + (trb->ctrl & DWC3_TRB_CTRL_LST)) return 1; return 0;