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[81.47.145.233]) by smtp.gmail.com with ESMTPSA id i192sm1960129wmg.7.2019.01.29.03.35.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 29 Jan 2019 03:35:20 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, gregkh@linuxfoundation.org, mark.rutland@arm.com, kishon@ti.com, jackp@codeaurora.org, andy.gross@linaro.org, swboyd@chromium.org Cc: shawn.guo@linaro.org, vkoul@kernel.org, bjorn.andersson@linaro.org, khasim.mohammed@linaro.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: Add Qualcomm USB Super-Speed PHY bindings Date: Tue, 29 Jan 2019 12:35:14 +0100 Message-Id: <1548761715-4004-2-git-send-email-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548761715-4004-1-git-send-email-jorge.ramirez-ortiz@linaro.org> References: <1548761715-4004-1-git-send-email-jorge.ramirez-ortiz@linaro.org> Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Binding description for Qualcomm's Synopsys 1.0.0 super-speed PHY controller embedded in QCS404. Based on Sriharsha Allenki's original definitions. Signed-off-by: Jorge Ramirez-Ortiz --- .../devicetree/bindings/usb/qcom,usb-ssphy.txt | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt diff --git a/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt new file mode 100644 index 0000000..8ef6e39 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/qcom,usb-ssphy.txt @@ -0,0 +1,73 @@ +Qualcomm Synopsys 1.0.0 SS phy controller +=========================================== + +Synopsys 1.0.0 ss phy controller supports SS usb connectivity on Qualcomm +chipsets + +Required properties: + +- compatible: + Value type: + Definition: Should contain "qcom,usb-ssphy". + +- reg: + Value type: + Definition: USB PHY base address and length of the register map. + +- #phy-cells: + Value type: + Definition: Should be 0. See phy/phy-bindings.txt for details. + +- clocks: + Value type: + Definition: See clock-bindings.txt section "consumers". List of + three clock specifiers for reference, phy core and + pipe clocks. + +- clock-names: + Value type: + Definition: Names of the clocks in 1-1 correspondence with the "clocks" + property. Must contain "ref", "phy" and "pipe". + +- vdd-supply: + Value type: + Definition: phandle to the regulator VDD supply node. + +- vdda1p8-supply: + Value type: + Definition: phandle to the regulator 1.8V supply node. + + +Optional child nodes: + +- vbus-supply: + Value type: + Definition: phandle to the VBUS supply node. + +- resets: + Value type: + Definition: See reset.txt section "consumers". PHY reset specifiers + for phy core and COR resets. + +- reset-names: + Value type: + Definition: Names of the resets in 1-1 correspondence with the "resets" + property. Must contain "com" and "phy". + +Example: + +usb3_phy: phy@78000 { + compatible = "qcom,usb-ssphy"; + reg = <0x78000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "phy", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; + vbus-supply = <&usb3_vbus_reg>; +};