From patchwork Mon Mar 11 11:11:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 10847329 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C376F139A for ; Mon, 11 Mar 2019 11:13:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AF54B28F88 for ; Mon, 11 Mar 2019 11:13:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A3B1928F90; Mon, 11 Mar 2019 11:13:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 265A828F88 for ; Mon, 11 Mar 2019 11:13:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727374AbfCKLNL (ORCPT ); Mon, 11 Mar 2019 07:13:11 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12888 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726605AbfCKLNL (ORCPT ); Mon, 11 Mar 2019 07:13:11 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 11 Mar 2019 04:13:10 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 11 Mar 2019 04:13:09 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 11 Mar 2019 04:13:09 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 11 Mar 2019 11:13:08 +0000 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 11 Mar 2019 11:13:08 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 11 Mar 2019 11:13:08 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.65.118]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 11 Mar 2019 04:13:08 -0700 From: Nagarjuna Kristam To: , , , CC: , , "Nagarjuna Kristam" Subject: [PATCH V2 4/8] dt-bindings: usb: Add NVIDIA Tegra XUSB device mode controller binding Date: Mon, 11 Mar 2019 16:41:52 +0530 Message-ID: <1552302716-18554-5-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552302716-18554-1-git-send-email-nkristam@nvidia.com> References: <1552302716-18554-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1552302790; bh=Ew6vwsZ7amAYoQvg3/VfZOZ2zU2m1xACElaRS3F/18g=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=j+0RcRROSJmSuzA4kofKC79S9wgEvLDO0nMQ3fksNY/8PywDkViOuMr9hw7ltHSY9 nog4nfyE7i1vof4Z2ZcmJHHv7HSGY0ywafKIpcq/zod+Z4t6rI/nSmg1paUQck+tDz Akq3GHhs7AOYWyLFzRsJF2q/FqnD+kQ/Q9D6v8AY9Fot31QCkzJO3D8b48n6S9VDJb OsbecYz52+HYl5I76bTWxrrxr23Dwx4f+Wpcf3Bku834JVW88LYcc9/MFmqAiy14+Y Ae2ul0VazfGRdhz6gln9v5NtyNLNMBleql9GsVD/z2iuT8VNUMdz4cgHy4iEoHtjtD lu/Or/gw4zR+Q== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device-tree binding documentation for the XUSB device mode controller present on tegra210 SoC. This controller supports USB 3.0 specification Based on work by Andrew Bresticker . Signed-off-by: Nagarjuna Kristam --- .../devicetree/bindings/usb/nvidia,tegra-xudc.txt | 105 +++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.txt diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.txt new file mode 100644 index 0000000..990655d --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.txt @@ -0,0 +1,105 @@ +Device tree binding for NVIDIA Tegra XUSB device mode controller (XUDC) +======================================================================= + +The Tegra XUDC controller supports both USB 2.0 HighSpeed/FullSpeed and +USB 3.0 SuperSpeed protocols. + +Required properties: +-------------------- +- compatible: For Tegra210, must contain "nvidia,tegra210-xudc". +- reg: Must contain the base and length of the XUSB device registers, XUSB device + PCI Config registers and XUSB device controller registers. +- interrupts: Must contain the XUSB device interrupt +- clocks: Must contain an entry for ell clocks used. + See ../clock/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - xusb_device + - xusb_ss + - xusb_ss_src + - xusb_hs_src + - xusb_fs_src +- nvidia,xusb-padctl: phandle to the XUSB pad controller that is used to + configure the USB pads used by the XUDC controller +- power-domains: A list of PM domain specifiers that reference each power-domain + used by the XUSB device mode controller. This list must comprise of a specifier + for the XUSBA and XUSBB power-domains. See ../power/power_domain.txt and + ../arm/tegra/nvidia,tegra20-pmc.txt for details. +- power-domain-names: A list of names that represent each of the specifiers in + the 'power-domains' property. Must include 'xusb_ss' and 'xusb_device' + +For Tegra210: +- avddio-usb-supply: PCIe/USB3 analog logic power supply. Must supply 1.05 V. +- hvdd-usb-supply: USB controller power supply. Must supply 3.3 V. +- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V. + +- phys: Must contain an entry for each entry in phy-names. + See ../phy/phy-bindings.txt for details. +- extcon-usb: Must contains an extcon-usb entry which detects + USB VBUS pin. See ../extcon/extcon-usb-gpio.txt for details. + +Optional properties: +-------------------- +- phy-names: Should include an entry for each PHY used by the controller. + Names must be "usb2", and "usb3" if support SuperSpeed device mode. + - "usb3" phy, SuperSpeed (SSTX+/SSTX-/SSRX+/SSRX-) data lines + - "usb2" phy, USB 2.0 (D+/D-) data lines + +Example: +-------- + pmc: pmc@7000e400 { + compatible = "nvidia,tegra210-pmc"; + reg = <0x0 0x7000e400 0x0 0x400>; + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + + powergates { + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; + resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; + #power-domain-cells = <0>; + }; + + pd_xusbdev: xusbb { + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; + resets = <&tegra_car 95>; + #power-domain-cells = <0>; + }; + }; + }; + + xudc@700d0000 { + compatible = "nvidia,tegra210-xudc"; + reg = <0x0 0x700d0000 0x0 0x8000>, + <0x0 0x700d8000 0x0 0x1000>, + <0x0 0x700d9000 0x0 0x1000>; + + interrupts = <0 44 0x4>; + + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, + <&tegra_car TEGRA210_CLK_XUSB_SS>, + <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>; + clock-names = "xusb_device", "xusb_ss", "xusb_ss_src", + "xusb_hs_src", "xusb_fs_src"; + + power-domains = <&pd_xusbdev>, <&pd_xusbss>; + power-domain-names = "xusb_device", "xusb_ss"; + + nvidia,xusb-padctl = <&padctl>; + + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>; + phy-names = "usb2; + + avddio-usb-supply = <&vdd_pex_1v05>; + hvdd-usb-supply = <&vdd_3v3_sys>; + avdd-pll-utmip-supply = <&vdd_1v8>; + + extcon = <&extcon_usb>; + }; + + extcon_usb: extcon_vbus { + compatible = "linux,extcon-usb-gpio"; + vbus-gpio = <&gpio TEGRA_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + }; +