From patchwork Fri Jul 5 11:41:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 11032495 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5F03C13B1 for ; Fri, 5 Jul 2019 11:42:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4D70228A45 for ; Fri, 5 Jul 2019 11:42:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 41FA228A4B; Fri, 5 Jul 2019 11:42:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BBBDE28A45 for ; Fri, 5 Jul 2019 11:42:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728799AbfGELmM (ORCPT ); Fri, 5 Jul 2019 07:42:12 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:3032 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728783AbfGELmL (ORCPT ); Fri, 5 Jul 2019 07:42:11 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 05 Jul 2019 04:42:05 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 05 Jul 2019 04:42:09 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 05 Jul 2019 04:42:09 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 5 Jul 2019 11:42:08 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 5 Jul 2019 11:42:08 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.65.118]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 05 Jul 2019 04:42:08 -0700 From: Nagarjuna Kristam To: , , , , , CC: , , , Nagarjuna Kristam Subject: [Patch V5 4/8] dt-bindings: usb: Add NVIDIA Tegra XUSB device mode controller binding Date: Fri, 5 Jul 2019 17:11:47 +0530 Message-ID: <1562326911-26855-5-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1562326911-26855-1-git-send-email-nkristam@nvidia.com> References: <1562326911-26855-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1562326925; bh=tJjxrDZHyaOfxCev2hs2Oi1CkYbPK8N4puD0fmur6NM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=QS9tNIIPh53vUaWxh/tnb510hhs3bDIs6nVoG3yB3vAl4LrJHulMQQwzO/wfEkls9 VAVCo+Og7xTFqYBftK6mCwdxqs5pEydMvNDcZwwjOtvFKXGHWPcICNsdM9Yolmhh35 4BJuZtF7gamQGGjuqhCgyYQYpQm1tpOfz13R1zmXzfeDvtHH8e2dE2G8gB79CrqEyr QX6sbEQbY4KRYCEQn9Jf1WYyuJM86KXLgkYv+51BprLPNzZxbPQhfgfmFZf6usbzHP whyHKtLmx9gJOFWLh26gcq+Y+FxOR5jBFj5elAZNWdJ7/VMOBMOFOvhXzxTyxnMv5T zmsBowU4fAltA== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add device-tree binding documentation for the XUSB device mode controller present on Tegra210 SoC. This controller supports the USB 3.0 specification. Signed-off-by: Nagarjuna Kristam Reviewed-by: JC Kuo --- .../devicetree/bindings/usb/nvidia,tegra-xudc.txt | 110 +++++++++++++++++++++ 1 file changed, 110 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.txt diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.txt new file mode 100644 index 0000000..c6a1b81 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.txt @@ -0,0 +1,110 @@ +Device tree binding for NVIDIA Tegra XUSB device mode controller (XUDC) +======================================================================= + +The Tegra XUDC controller supports both USB 2.0 HighSpeed/FullSpeed and +USB 3.0 SuperSpeed protocols. + +Required properties: +-------------------- +- compatible: For Tegra210, must contain "nvidia,tegra210-xudc". +- reg: Must contain the base and length of all registers used. +- interrupts: Must contain the XUSB device interrupt. +- clocks: Must contain an entry for all clocks used. + See ../clock/clock-bindings.txt for details. +- clock-names: Must include the following entries: + - dev: Clock to enable core XUSB dev clock. + - ss: Clock to enable XUSB super speed clock. + - ss_src: Clock to enable XUSB super speed dev clock. + - hs_src: Clock to enable XUSB high speed dev clock. + - fs_src: Clock to enable XUSB full speed dev clock. +- nvidia,xusb-padctl: phandle to the XUSB pad controller that is used to + configure the USB pads used by the XUDC controller. +- power-domains: A list of PM domain specifiers that reference each power-domain + used by the XUSB device mode controller. This list must comprise of a specifier + for the XUSBA and XUSBB power-domains. See ../power/power_domain.txt and + ../arm/tegra/nvidia,tegra20-pmc.txt for details. +- power-domain-names: A list of names that represent each of the specifiers in + the 'power-domains' property. Must include 'ss' and 'dev'. +- phys: Must contain an entry for each entry in phy-names. + See ../phy/phy-bindings.txt for details. +- phy-names: Should include an entry for each PHY used by the controller. + Names must be "usb2", and "usb3" if support SuperSpeed device mode. + - "usb3" phy, SuperSpeed (SSTX+/SSTX-/SSRX+/SSRX-) data lines. + - "usb2" phy, USB 2.0 (D+/D-) data lines. + +For Tegra210: +- reg-names: Must include the following entries: + - base: XUSB device controller registers. + - fpci: XUSB device PCI Config registers. + - ipfs: XUSB device registers. +- avddio-usb-supply: PCIe/USB3 analog logic power supply. Must supply 1.05 V. +- hvdd-usb-supply: USB controller power supply. Must supply 3.3 V. + + +Optional properties: +-------------------- +- usb-role-switch: boolean property to indicate use of USB Role Switch driver. + +Sub-nodes: +---------- +- The port would be added as subnode if use "usb-role-switch" property. + see graph.txt. + +Example: +-------- + pmc: pmc@7000e400 { + compatible = "nvidia,tegra210-pmc"; + reg = <0x0 0x7000e400 0x0 0x400>; + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + + powergates { + pd_xusbss: xusba { + clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; + resets = <&tegra_car 156>; + #power-domain-cells = <0>; + }; + + pd_xusbdev: xusbb { + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; + resets = <&tegra_car 95>; + #power-domain-cells = <0>; + }; + }; + }; + + xudc@700d0000 { + compatible = "nvidia,tegra210-xudc"; + reg = <0x0 0x700d0000 0x0 0x8000>, + <0x0 0x700d8000 0x0 0x1000>, + <0x0 0x700d9000 0x0 0x1000>; + reg-names = "base", "fpci", "ipfs"; + + interrupts = ; + + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, + <&tegra_car TEGRA210_CLK_XUSB_SS>, + <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>; + clock-names = "dev", "ss", "ss_src", "hs_src", "fs_src"; + + power-domains = <&pd_xusbdev>, <&pd_xusbss>; + power-domain-names = "dev", "ss"; + + nvidia,xusb-padctl = <&padctl>; + + phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>; + phy-names = "usb2; + + avddio-usb-supply = <&vdd_pex_1v05>; + hvdd-usb-supply = <&vdd_3v3_sys>; + + usb-role-switch; + port { + usb_role_switch: endpoint@0 { + remote-endpoint = <&bconn_ep>; + }; + }; + + };