From patchwork Fri Jul 5 11:41:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 11032497 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DCEAF13B1 for ; Fri, 5 Jul 2019 11:42:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CD94828A45 for ; Fri, 5 Jul 2019 11:42:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C173428A4B; Fri, 5 Jul 2019 11:42:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 71C8928A45 for ; Fri, 5 Jul 2019 11:42:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728802AbfGELmN (ORCPT ); Fri, 5 Jul 2019 07:42:13 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:18415 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728783AbfGELmN (ORCPT ); Fri, 5 Jul 2019 07:42:13 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 05 Jul 2019 04:42:16 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 05 Jul 2019 04:42:12 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 05 Jul 2019 04:42:12 -0700 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 5 Jul 2019 11:42:11 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 5 Jul 2019 11:42:11 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.65.118]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 05 Jul 2019 04:42:11 -0700 From: Nagarjuna Kristam To: , , , , , CC: , , , Nagarjuna Kristam Subject: [Patch V5 5/8] arm64: tegra: Add xudc node for Tegra210 Date: Fri, 5 Jul 2019 17:11:48 +0530 Message-ID: <1562326911-26855-6-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1562326911-26855-1-git-send-email-nkristam@nvidia.com> References: <1562326911-26855-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1562326936; bh=C7vgssYDUBLI4OLMpwWFocUY6137QecNwq9dTK257FY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=owk0hQSrfp5X5xhJ3tEuFuwvfhZrKP99cUogLc1anfQF/mwiKDQBTRGnwTaA3geVs J8ex8XtKpmX4BR1/1qhpmWPpznwKe3OeR4dPhlgnqG6mgmN7lfOKlJbmGTKAlmuOVP iIllWRxrMqLXJBEbro5rboVW7TSeh5Yh792+EDTmEUn0IH0LOSdTbV94xN/F3xCdFD IHJAMfjBaYEo6yKAixlQyzAqixX34dXy4hn01roEAb1Dza/t3CFpS5bnw8KzY6wJoG CMtAEKKYIqj51Zwe1Pqf7veD3UfE5dk6GTrhFTGo/kyeX+3EwynrTnOZG00y3mrghZ T05v3YWkfcpHQ== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra210 has one XUSB device mode controller, which can be operated HS and SS modes. Add DT support for XUSB device mode controller. Signed-off-by: Nagarjuna Kristam Reviewed-by: JC Kuo --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 6597531..26188ac 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1203,6 +1203,25 @@ status = "disabled"; }; + xudc@700d0000 { + compatible = "nvidia,tegra210-xudc"; + reg = <0x0 0x700d0000 0x0 0x8000>, + <0x0 0x700d8000 0x0 0x1000>, + <0x0 0x700d9000 0x0 0x1000>; + reg-names = "base", "fpci", "ipfs"; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, + <&tegra_car TEGRA210_CLK_XUSB_SS>, + <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>; + clock-names = "dev", "ss", "ss_src", "hs_src", "fs_src"; + power-domains = <&pd_xusbdev>, <&pd_xusbss>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&padctl>; + status = "disabled"; + }; + mipi: mipi@700e3000 { compatible = "nvidia,tegra210-mipi"; reg = <0x0 0x700e3000 0x0 0x100>;