| Message ID | 1576636944-196192-3-git-send-email-hanjie.lin@amlogic.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: meson: Add support for USB on Amlogic A1 | expand |
Hi, On 18/12/2019 03:42, Hanjie Lin wrote: > The Amlogic A1 SoC Family embeds 1 USB Controllers: > - a DWC3 IP configured as Host for USB2 and USB3 > > A glue connects the controllers to the USB2 PHY of A1 SoC. > > Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com> > Signed-off-by: Yue Wang <yue.wang@amlogic.com> > --- > .../bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml | 32 ++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml > index 4efb77b..9740027 100644 > --- a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml > +++ b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml > @@ -9,6 +9,8 @@ title: Amlogic Meson G12A DWC3 USB SoC Controller Glue > > maintainers: > - Neil Armstrong <narmstrong@baylibre.com> > + - Hanjie Lin <hanjie.lin@amlogic.com> > + - Yue Wang <yue.wang@amlogic.com> > > description: | > The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3 > @@ -22,10 +24,14 @@ description: | > The DWC3 Glue controls the PHY routing and power, an interrupt line is > connected to the Glue to serve as OTG ID change detection. > > + The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in > + host-only mode. > + > properties: > compatible: > enum: > - amlogic,meson-g12a-usb-ctrl > + - amlogic,meson-a1-usb-ctrl > > ranges: true > > @@ -124,4 +130,30 @@ examples: > snps,quirk-frame-length-adjustment; > }; > }; > + - | > + usb: usb@ffe09000 { > + status = "okay"; > + compatible = "amlogic,meson-a1-usb-ctrl"; > + reg = <0x0 0xffe09000 0x0 0xa0>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > > + clocks = <&clkc_periphs CLKID_USB_CTRL>, > + <&clkc_periphs CLKID_USB_BUS>, > + <&clkc_periphs CLKID_XTAL_USB_PHY>, > + <&clkc_periphs CLKID_XTAL_USB_CTRL>; > + clock-names = "usb_ctrl", "usb_bus", "xtal_usb_phy", "xtal_usb_ctrl"; > + resets = <&reset RESET_USBCTRL>; > + phys = <&usb2_phy0>; > + phy-names = "usb2-phy0"; > + > + dwc3: usb@ff400000 { > + compatible = "snps,dwc3"; > + reg = <0x0 0xff400000 0x0 0x100000>; > + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; > + dr_mode = "host"; > + snps,dis_u2_susphy_quirk; > + snps,quirk-frame-length-adjustment = <0x20>; > + }; > + }; > I doubt this passed the dt_binding_check ! Please add the clock-names only for amlogic,meson-a1-usb-ctrl, set the phys maxItems to 1 for amlogic,meson-a1-usb-ctrl, and set dr_mode as host in the example or make it required only for amlogic,meson-g12a-usb-ctrl. Neil
On 2019/12/18 21:13, Neil Armstrong wrote: > Hi, > > On 18/12/2019 03:42, Hanjie Lin wrote: >> The Amlogic A1 SoC Family embeds 1 USB Controllers: >> - a DWC3 IP configured as Host for USB2 and USB3 >> >> A glue connects the controllers to the USB2 PHY of A1 SoC. >> >> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com> >> Signed-off-by: Yue Wang <yue.wang@amlogic.com> >> --- >> .../bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml | 32 ++++++++++++++++++++++ >> 1 file changed, 32 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml >> index 4efb77b..9740027 100644 >> --- a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml >> +++ b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml >> @@ -9,6 +9,8 @@ title: Amlogic Meson G12A DWC3 USB SoC Controller Glue >> >> maintainers: >> - Neil Armstrong <narmstrong@baylibre.com> >> + - Hanjie Lin <hanjie.lin@amlogic.com> >> + - Yue Wang <yue.wang@amlogic.com> >> >> description: | >> The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3 >> @@ -22,10 +24,14 @@ description: | >> The DWC3 Glue controls the PHY routing and power, an interrupt line is >> connected to the Glue to serve as OTG ID change detection. >> >> + The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in >> + host-only mode. >> + >> properties: >> compatible: >> enum: >> - amlogic,meson-g12a-usb-ctrl >> + - amlogic,meson-a1-usb-ctrl >> >> ranges: true >> >> @@ -124,4 +130,30 @@ examples: >> snps,quirk-frame-length-adjustment; >> }; >> }; >> + - | >> + usb: usb@ffe09000 { >> + status = "okay"; >> + compatible = "amlogic,meson-a1-usb-ctrl"; >> + reg = <0x0 0xffe09000 0x0 0xa0>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> >> + clocks = <&clkc_periphs CLKID_USB_CTRL>, >> + <&clkc_periphs CLKID_USB_BUS>, >> + <&clkc_periphs CLKID_XTAL_USB_PHY>, >> + <&clkc_periphs CLKID_XTAL_USB_CTRL>; >> + clock-names = "usb_ctrl", "usb_bus", "xtal_usb_phy", "xtal_usb_ctrl"; >> + resets = <&reset RESET_USBCTRL>; >> + phys = <&usb2_phy0>; >> + phy-names = "usb2-phy0"; >> + >> + dwc3: usb@ff400000 { >> + compatible = "snps,dwc3"; >> + reg = <0x0 0xff400000 0x0 0x100000>; >> + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; >> + dr_mode = "host"; >> + snps,dis_u2_susphy_quirk; >> + snps,quirk-frame-length-adjustment = <0x20>; >> + }; >> + }; >> > > I doubt this passed the dt_binding_check ! > > > Please add the clock-names only for amlogic,meson-a1-usb-ctrl, > set the phys maxItems to 1 for amlogic,meson-a1-usb-ctrl, > and set dr_mode as host in the example or make it required only > for amlogic,meson-g12a-usb-ctrl. > > Neil > > . > Hi Neil, It does report errors by dt_binding_check, I will check the list again. Thanks Hanjie.lin
diff --git a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml index 4efb77b..9740027 100644 --- a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml +++ b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml @@ -9,6 +9,8 @@ title: Amlogic Meson G12A DWC3 USB SoC Controller Glue maintainers: - Neil Armstrong <narmstrong@baylibre.com> + - Hanjie Lin <hanjie.lin@amlogic.com> + - Yue Wang <yue.wang@amlogic.com> description: | The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3 @@ -22,10 +24,14 @@ description: | The DWC3 Glue controls the PHY routing and power, an interrupt line is connected to the Glue to serve as OTG ID change detection. + The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in + host-only mode. + properties: compatible: enum: - amlogic,meson-g12a-usb-ctrl + - amlogic,meson-a1-usb-ctrl ranges: true @@ -124,4 +130,30 @@ examples: snps,quirk-frame-length-adjustment; }; }; + - | + usb: usb@ffe09000 { + status = "okay"; + compatible = "amlogic,meson-a1-usb-ctrl"; + reg = <0x0 0xffe09000 0x0 0xa0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&clkc_periphs CLKID_USB_CTRL>, + <&clkc_periphs CLKID_USB_BUS>, + <&clkc_periphs CLKID_XTAL_USB_PHY>, + <&clkc_periphs CLKID_XTAL_USB_CTRL>; + clock-names = "usb_ctrl", "usb_bus", "xtal_usb_phy", "xtal_usb_ctrl"; + resets = <&reset RESET_USBCTRL>; + phys = <&usb2_phy0>; + phy-names = "usb2-phy0"; + + dwc3: usb@ff400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff400000 0x0 0x100000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,dis_u2_susphy_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + }; + };