From patchwork Tue Feb 4 11:17:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 11364451 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5CAC513A4 for ; Tue, 4 Feb 2020 11:19:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3B55221D7D for ; Tue, 4 Feb 2020 11:19:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="D2eA+DKw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727539AbgBDLTw (ORCPT ); Tue, 4 Feb 2020 06:19:52 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:17838 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727538AbgBDLTu (ORCPT ); Tue, 4 Feb 2020 06:19:50 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 04 Feb 2020 03:19:35 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 04 Feb 2020 03:19:49 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 04 Feb 2020 03:19:49 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 4 Feb 2020 11:19:49 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 4 Feb 2020 11:19:49 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 04 Feb 2020 03:19:48 -0800 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V4 15/19] arm64: tegra: Add xudc node for Tegra210 Date: Tue, 4 Feb 2020 16:47:01 +0530 Message-ID: <1580815025-10915-16-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580815025-10915-1-git-send-email-nkristam@nvidia.com> References: <1580815025-10915-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1580815175; bh=wysAX+a4vH2ybq/MDBREdQSJaojkDJ/8xjNH5pqjdsg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=D2eA+DKwDAmPKsBMzM6uJFBcLjA4x5DKY8MGuHieIy4ArOqIsmZS2Wl0HRyJGkAi6 zwsImuzb3Uw0/b7KHvxQSED+C3qj/YFa70/As9Gs2lBospKwwh0cDibdsdWX0lptyt Yl2Hc5QgNVaxFErZCKz7hdNuyaiJ+2sO5OVrkoL0lpvX2pCEKF3CwUWnND7Eg6TT3Z 6dp0Z1RJz2UYhNOWA8bfOiPAyU9AQUe+maW2wUQx0/Dm9OYCzjcY6bxA4srgisYGQY LkFsy47zePZMoGPAAurFBs/b6R6WjWFOPxUyz7U21s8+G51obiyOc7qBYuD+PcK9Lo /ugbkJOooIoAw== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Tegra210 has one XUSB device mode controller, which can be operated HS and SS modes. Add DT entry for XUSB device mode controller. Signed-off-by: Nagarjuna Kristam --- V2-V4: - Updated clocks and clock-names sequence as per change in bindings doc. --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 48c6325..dfce47b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1207,6 +1207,25 @@ status = "disabled"; }; + usb@700d0000 { + compatible = "nvidia,tegra210-xudc"; + reg = <0x0 0x700d0000 0x0 0x8000>, + <0x0 0x700d8000 0x0 0x1000>, + <0x0 0x700d9000 0x0 0x1000>; + reg-names = "base", "fpci", "ipfs"; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, + <&tegra_car TEGRA210_CLK_XUSB_SS>, + <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; + clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; + power-domains = <&pd_xusbdev>, <&pd_xusbss>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&padctl>; + status = "disabled"; + }; + mipi: mipi@700e3000 { compatible = "nvidia,tegra210-mipi"; reg = <0x0 0x700e3000 0x0 0x100>;