From patchwork Tue Feb 18 01:54:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjie Lin X-Patchwork-Id: 11387741 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3C06817E8 for ; Tue, 18 Feb 2020 01:54:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 28E6A22B48 for ; Tue, 18 Feb 2020 01:54:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726303AbgBRByw (ORCPT ); Mon, 17 Feb 2020 20:54:52 -0500 Received: from mail-sh.amlogic.com ([58.32.228.43]:37711 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726171AbgBRByv (ORCPT ); Mon, 17 Feb 2020 20:54:51 -0500 Received: from droid10.amlogic.com (10.18.11.213) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.1591.10; Tue, 18 Feb 2020 09:55:09 +0800 From: Hanjie Lin To: Kishon Vijay Abraham I , Jerome Brunet , Neil Armstrong , Rob Herring , Greg Kroah-Hartman , Kevin Hilman CC: Hanjie Lin , Yue Wang , , , , , Carlo Caione , Michael Turquette , Stephen Boyd , Martin Blumenstingl , Liang Yang , Jianxin Pan , Qiufang Dai , Jian Hu , Victor Wan , Xingyu Chen Subject: [PATCH v9 3/3] arm64: dts: meson: a1: Enable USB2 PHY and DWC3 controller Date: Tue, 18 Feb 2020 09:54:19 +0800 Message-ID: <1581990859-135234-4-git-send-email-hanjie.lin@amlogic.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581990859-135234-1-git-send-email-hanjie.lin@amlogic.com> References: <1581990859-135234-1-git-send-email-hanjie.lin@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.213] Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Enable USB2 PHY and DWC3 controller for Meson A1 SoC. Signed-off-by: Yue Wang Signed-off-by: Hanjie Lin Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 43 +++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 6fdc0dd..3b7ca50 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -6,6 +6,9 @@ #include #include #include +#include +#include +#include / { compatible = "amlogic,a1"; @@ -100,6 +103,17 @@ #power-domain-cells = <1>; status = "okay"; }; + + usb2_phy1: phy@40000 { + compatible = "amlogic,a1-usb2-phy"; + clocks = <&clkc_periphs CLKID_XTAL_USB_PHY>; + clock-names = "xtal"; + reg = <0x0 0x40000 0x0 0x2000>; + resets = <&reset RESET_USBPHY>; + reset-names = "phy"; + #phy-cells = <0>; + power-domains = <&pwrc PWRC_USB_ID>; + }; }; gic: interrupt-controller@ff901000 { @@ -114,6 +128,35 @@ #interrupt-cells = <3>; #address-cells = <0>; }; + + usb: usb@ffe09000 { + status = "disabled"; + compatible = "amlogic,meson-a1-usb-ctrl"; + reg = <0x0 0xffe09000 0x0 0xa0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&clkc_periphs CLKID_USB_CTRL>, + <&clkc_periphs CLKID_USB_BUS>, + <&clkc_periphs CLKID_XTAL_USB_CTRL>; + clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl"; + resets = <&reset RESET_USBCTRL>; + + dr_mode = "host"; + + phys = <&usb2_phy1>; + phy-names = "usb2-phy1"; + + dwc3: usb@ff400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff400000 0x0 0x100000>; + interrupts = ; + dr_mode = "host"; + snps,dis_u2_susphy_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + }; + }; }; timer {