| Message ID | 1587022460-31988-3-git-send-email-nkristam@nvidia.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Tegra XUDC support on Tegra194 Soc | expand |
On Thu, Apr 16, 2020 at 01:04:18PM +0530, Nagarjuna Kristam wrote: > Tegra194 has one XUSB device mode controller, which can be operated > HS and SS modes. Add DT entry for XUSB device mode controller > > Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> > --- > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) Looks good to me, I'll pick this up into the Tegra tree. Thierry
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index f4ede86..e1ae01c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -644,6 +644,24 @@ }; }; + usb@3550000 { + compatible = "nvidia,tegra194-xudc"; + reg = <0x03550000 0x8000>, + <0x03558000 0x1000>; + reg-names = "base", "fpci"; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, + <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA194_CLK_XUSB_SS>, + <&bpmp TEGRA194_CLK_XUSB_FS>; + clock-names = "dev", "ss", "ss_src", "fs_src"; + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, + <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&xusb_padctl>; + status = "disabled"; + }; + usb@3610000 { compatible = "nvidia,tegra194-xusb"; reg = <0x03610000 0x40000>,
Tegra194 has one XUSB device mode controller, which can be operated HS and SS modes. Add DT entry for XUSB device mode controller Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)