From patchwork Mon May 4 06:34:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 11525121 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 29C6514B4 for ; Mon, 4 May 2020 06:33:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1266720746 for ; Mon, 4 May 2020 06:33:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="h1qhi0oT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727838AbgEDGdh (ORCPT ); Mon, 4 May 2020 02:33:37 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:19627 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726743AbgEDGdh (ORCPT ); Mon, 4 May 2020 02:33:37 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 03 May 2020 23:31:29 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 03 May 2020 23:33:36 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 03 May 2020 23:33:36 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 4 May 2020 06:33:36 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 4 May 2020 06:33:36 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sun, 03 May 2020 23:33:35 -0700 From: Nagarjuna Kristam To: , , , , CC: , , , Nagarjuna Kristam Subject: [PATCH V2 2/3] usb: gadget: tegra-xudc: Add Tegra194 support Date: Mon, 4 May 2020 12:04:40 +0530 Message-ID: <1588574081-23160-3-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1588574081-23160-1-git-send-email-nkristam@nvidia.com> References: <1588574081-23160-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1588573889; bh=B/ZJ2skrpSXMvGZJlSiYl3vlRxjANNqiNcO1sk0Y1NY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=h1qhi0oTWOd5yKzgJeIgfCsb7GvnGBWGhN4FmIGV8K2+a2qGoeuyFRgpOPke7Ur1D EHDYmBC1H6R/BJPTGaVJ1TNCekvREuDGOhUgt88OBkk5+Ig9lRp7mYZ2gxlN663nZk gjvFb8451NVcnxdQalQ4dhJNEcH2gzSDiRQpu0xC5JzKaxu8dCjPmEYvA13XaVQOrp Boau1yt4k2GY48Y65tKZaq6sIfGT9rQJDUzWhN11TS67x2oHhd0iSJv56E5n3lU6Co KY15RFu9Bw10lVqIboXz0dj9eCLrgT2OrFPMLmde8FKz1jxIjbL3uApJYdsEiQMGX1 DATID44yy/10w== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org This commit adds support for XUSB device mode controller support on Tegra194 SoC. This is very similar to the existing Tegra186 XUDC, with lpm support added in addition. Signed-off-by: Nagarjuna Kristam Acked-by: Thierry Reding --- V2: - Added Acked-by updates to commit message. - Re-used T186 clock names for T194 SoC data. --- drivers/usb/gadget/udc/tegra-xudc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c index 52a6add..04c6a06 100644 --- a/drivers/usb/gadget/udc/tegra-xudc.c +++ b/drivers/usb/gadget/udc/tegra-xudc.c @@ -3522,6 +3522,19 @@ static struct tegra_xudc_soc tegra186_xudc_soc_data = { .has_ipfs = false, }; +static struct tegra_xudc_soc tegra194_xudc_soc_data = { + .clock_names = tegra186_xudc_clock_names, + .num_clks = ARRAY_SIZE(tegra186_xudc_clock_names), + .num_phys = 4, + .u1_enable = true, + .u2_enable = true, + .lpm_enable = true, + .invalid_seq_num = false, + .pls_quirk = false, + .port_reset_quirk = false, + .has_ipfs = false, +}; + static const struct of_device_id tegra_xudc_of_match[] = { { .compatible = "nvidia,tegra210-xudc", @@ -3531,6 +3544,10 @@ static const struct of_device_id tegra_xudc_of_match[] = { .compatible = "nvidia,tegra186-xudc", .data = &tegra186_xudc_soc_data }, + { + .compatible = "nvidia,tegra194-xudc", + .data = &tegra194_xudc_soc_data + }, { } }; MODULE_DEVICE_TABLE(of, tegra_xudc_of_match);