From patchwork Thu May 14 06:22:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nagarjuna Kristam X-Patchwork-Id: 11548015 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BA85E60D for ; Thu, 14 May 2020 06:23:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9F2FD2070A for ; Thu, 14 May 2020 06:23:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="iFNFUn02" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726179AbgENGXL (ORCPT ); Thu, 14 May 2020 02:23:11 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:17921 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726146AbgENGXJ (ORCPT ); Thu, 14 May 2020 02:23:09 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 13 May 2020 23:21:53 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 13 May 2020 23:23:08 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 13 May 2020 23:23:08 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 14 May 2020 06:23:08 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 14 May 2020 06:23:08 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.67.128]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 13 May 2020 23:23:07 -0700 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [PATCH V3 5/8] phy: tegra: xusb: Add soc ops API to enable UTMI PAD protection Date: Thu, 14 May 2020 11:52:40 +0530 Message-ID: <1589437363-16727-6-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589437363-16727-1-git-send-email-nkristam@nvidia.com> References: <1589437363-16727-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1589437313; bh=hRAaYo1odsG3KZvRAQDG5cZFxZ7IA38jiAjjskNrwBQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=iFNFUn02MPUT98y4tm5VpONx7Z3ZLRPwGL8M9AYgHdKxZAy5F7gJnibAqlFTAAQPu PVxmg37ShYAHHNVS4/3w8cPGsnj9vzLMd6v25luMuJxVaBaReG2Azc0KNnjZylF9pI 8r+mpeqNaUtNTJfJm8FrDOAimB1RLFMCftB3o8Fiod9UkISd2VcKVUosMnVDnb+M+H fOsel3aywbXHkfwTvlqgoAAhHviCg4wxQsw8/Cw850ffzgKoMDjFyUG4SABF0kZTPk ZvKsrJVu5Z2gJwZj5lYWUmXPDJWcn6nuXxKR0ZELqR9g+C/lPq+LNocpR3ZyvMTDON GMB+9v5/pVYFQ== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org When USB charger is enabled, UTMI PAD needs to be protected according to the direction and current level. Add support for the same on Tegra210 and Tegra186. Signed-off-by: Nagarjuna Kristam Acked-by: Thierry Reding --- V3: - Alligned function and its arguments. - Fixed other comments from Thierry. --- V2: - Commit message coorected. - Patch re-based. --- drivers/phy/tegra/xusb-tegra186.c | 40 +++++++++++++++++++++++++++++++++++++++ drivers/phy/tegra/xusb-tegra210.c | 32 +++++++++++++++++++++++++++++++ drivers/phy/tegra/xusb.h | 13 +++++++++++++ 3 files changed, 85 insertions(+) diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c index f862254..59b78a7 100644 --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c @@ -68,6 +68,13 @@ #define PORTX_SPEED_SUPPORT_MASK (0x3) #define PORT_SPEED_SUPPORT_GEN1 (0x0) +#define USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x84 + (x) * 0x40) +#define PD_VREG (1 << 6) +#define VREG_LEV(x) (((x) & 0x3) << 7) +#define VREG_DIR(x) (((x) & 0x3) << 11) +#define VREG_DIR_IN VREG_DIR(1) +#define VREG_DIR_OUT VREG_DIR(2) + #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40) #define HS_CURR_LEVEL(x) ((x) & 0x3f) #define TERM_SEL BIT(25) @@ -289,6 +296,37 @@ static void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy) usb2->powered_on = false; } +static void +tegra186_xusb_padctl_utmi_pad_set_protection(struct tegra_xusb_port *port, + int level, + enum tegra_vbus_dir dir) +{ + u32 value; + struct tegra_xusb_padctl *padctl = port->padctl; + unsigned int index = port->index; + + value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); + + if (level < 0) { + /* disable pad protection */ + value |= PD_VREG; + value &= ~VREG_LEV(~0); + value &= ~VREG_DIR(~0); + } else { + if (dir == TEGRA_VBUS_SOURCE) + value |= VREG_DIR_OUT; + else if (dir == TEGRA_VBUS_SINK) + value |= VREG_DIR_IN; + + value &= ~PD_VREG; + value &= ~VREG_DIR(~0); + value &= ~VREG_LEV(~0); + value |= VREG_LEV(level); + } + + padctl_writel(padctl, value, USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); +} + static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl, bool status) { @@ -935,6 +973,8 @@ static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = { .vbus_override = tegra186_xusb_padctl_vbus_override, .utmi_pad_power_on = tegra_phy_xusb_utmi_pad_power_on, .utmi_pad_power_down = tegra_phy_xusb_utmi_pad_power_down, + .utmi_pad_set_protection = + tegra186_xusb_padctl_utmi_pad_set_protection, }; #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c index caf0890..80c4349 100644 --- a/drivers/phy/tegra/xusb-tegra210.c +++ b/drivers/phy/tegra/xusb-tegra210.c @@ -74,6 +74,8 @@ #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL 0x1 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6) +#define USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(x) (((x) & 0x3) << 7) +#define USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_DIR(x) (((x) & 0x3) << 11) #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40) #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI (1 << 29) @@ -1116,6 +1118,34 @@ void tegra210_usb2_pad_power_down(struct phy *phy) usb2->powered_on = false; } +static void +tegra210_xusb_padctl_utmi_pad_set_protection(struct tegra_xusb_port *port, + int level, + enum tegra_vbus_dir dir) +{ + u32 value; + struct tegra_xusb_padctl *padctl = port->padctl; + unsigned int index = port->index; + + value = padctl_readl(padctl, + XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); + + if (level < 0) { + /* disable pad protection */ + value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18; + value &= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(~0); + value &= ~USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_DIR(~0); + } else { + value &= ~XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18; + value &= ~USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_DIR(~0); + value &= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(~0); + value |= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(level); + } + + padctl_writel(padctl, value, + XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index)); +} + static int tegra210_usb2_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) { @@ -2291,6 +2321,8 @@ static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops = { .utmi_port_reset = tegra210_utmi_port_reset, .utmi_pad_power_on = tegra210_usb2_pad_power_on, .utmi_pad_power_down = tegra210_usb2_pad_power_down, + .utmi_pad_set_protection = + tegra210_xusb_padctl_utmi_pad_set_protection, }; static const char * const tegra210_xusb_padctl_supply_names[] = { diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h index 6995fc4..475bcc6 100644 --- a/drivers/phy/tegra/xusb.h +++ b/drivers/phy/tegra/xusb.h @@ -259,6 +259,17 @@ to_sata_pad(struct tegra_xusb_pad *pad) */ struct tegra_xusb_port_ops; +/* + * Tegra OTG port VBUS direction: + * default (based on port capability) or + * as source or sink + */ +enum tegra_vbus_dir { + TEGRA_VBUS_DEFAULT, + TEGRA_VBUS_SOURCE, + TEGRA_VBUS_SINK +}; + struct tegra_xusb_port { struct tegra_xusb_padctl *padctl; struct tegra_xusb_lane *lane; @@ -398,6 +409,8 @@ struct tegra_xusb_padctl_ops { int (*utmi_port_reset)(struct phy *phy); void (*utmi_pad_power_on)(struct phy *phy); void (*utmi_pad_power_down)(struct phy *phy); + void (*utmi_pad_set_protection)(struct tegra_xusb_port *port, + int level, enum tegra_vbus_dir dir); }; struct tegra_xusb_padctl_soc {