| Message ID | 1594028699-1055-6-git-send-email-jun.li@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | add NXP imx8mp usb support | expand |
On Mon, Jul 06, 2020 at 05:44:59PM +0800, Li Jun wrote: > NXP imx8mp integrates 2 dwc3 3.30b IP and add some wakeup logic > to support low power mode, the glue layer is for this wakeup > functionality, which has a separated interrupt, can support > wakeup from U3 and connect events for host, and vbus wakeup for > device. > > Signed-off-by: Li Jun <jun.li@nxp.com> > --- > .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 87 ++++++++++++++++++++++ > 1 file changed, 87 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml > new file mode 100644 > index 0000000..823db058 > --- /dev/null > +++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml > @@ -0,0 +1,87 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2020 NXP > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP iMX8MP Soc USB Controller > + > +maintainers: > + - Li Jun <jun.li@nxp.com> > + > +properties: > + compatible: > + items: > + - const: fsl,imx8mp-dwc3 > + > + reg: > + maxItems: 1 > + description: Address and length of the register set for the wrapper of > + dwc3 core on the SOC. > + > + "#address-cells": > + enum: [ 1, 2 ] > + > + "#size-cells": > + enum: [ 1, 2 ] > + > + interrupts: > + maxItems: 1 > + description: The interrupt that is asserted when a wakeup event is > + received. > + > + clocks: > + description: > + A list of phandle and clock-specifier pairs for the clocks > + listed in clock-names. > + items: > + - description: system hsio root clock. > + - description: system bus AXI clock. > + - description: suspend clock, used for wakeup logic. > + > + clock-names: > + items: > + - const: hsio > + - const: bus > + - const: suspend > + > +# Required child node: > + > + dwc3: Needs to be a pattern with the unit-address. > + description: This is the node representing the DWC3 controller instance > + Documentation/devicetree/bindings/usb/dwc3.txt > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks Pretty sure you need a few more properties here... Add: additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/imx8mp-clock.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + usb3_0: usb@32f10100 { > + compatible = "fsl,imx8mp-dwc3"; > + reg = <0x32f10100 0x8>; > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > + <&clk IMX8MP_CLK_HSIO_AXI_DIV>, > + <&clk IMX8MP_CLK_USB_ROOT>; > + clock-names = "hsio", "bus", "suspend"; > + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; > + assigned-clock-rates = <500000000>; > + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + dwc3@38100000 { > + compatible = "snps,dwc3"; > + reg = <0x38100000 0x10000>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&usb3_phy0>, <&usb3_phy0>; > + phy-names = "usb2-phy", "usb3-phy"; > + }; > + }; > -- > 2.7.4 >
diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml new file mode 100644 index 0000000..823db058 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2020 NXP +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP iMX8MP Soc USB Controller + +maintainers: + - Li Jun <jun.li@nxp.com> + +properties: + compatible: + items: + - const: fsl,imx8mp-dwc3 + + reg: + maxItems: 1 + description: Address and length of the register set for the wrapper of + dwc3 core on the SOC. + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + interrupts: + maxItems: 1 + description: The interrupt that is asserted when a wakeup event is + received. + + clocks: + description: + A list of phandle and clock-specifier pairs for the clocks + listed in clock-names. + items: + - description: system hsio root clock. + - description: system bus AXI clock. + - description: suspend clock, used for wakeup logic. + + clock-names: + items: + - const: hsio + - const: bus + - const: suspend + +# Required child node: + + dwc3: + description: This is the node representing the DWC3 controller instance + Documentation/devicetree/bindings/usb/dwc3.txt + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + #include <dt-bindings/clock/imx8mp-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + usb3_0: usb@32f10100 { + compatible = "fsl,imx8mp-dwc3"; + reg = <0x32f10100 0x8>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "hsio", "bus", "suspend"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dwc3@38100000 { + compatible = "snps,dwc3"; + reg = <0x38100000 0x10000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy0>, <&usb3_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + }; + };
NXP imx8mp integrates 2 dwc3 3.30b IP and add some wakeup logic to support low power mode, the glue layer is for this wakeup functionality, which has a separated interrupt, can support wakeup from U3 and connect events for host, and vbus wakeup for device. Signed-off-by: Li Jun <jun.li@nxp.com> --- .../devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+)