From patchwork Fri Jun 14 09:35:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Chen X-Patchwork-Id: 10994773 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8519E1398 for ; Fri, 14 Jun 2019 09:34:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 762B827B13 for ; Fri, 14 Jun 2019 09:34:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6A5B127F4B; Fri, 14 Jun 2019 09:34:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA81427B13 for ; Fri, 14 Jun 2019 09:34:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727038AbfFNJeH (ORCPT ); Fri, 14 Jun 2019 05:34:07 -0400 Received: from inva021.nxp.com ([92.121.34.21]:53930 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726530AbfFNJeH (ORCPT ); Fri, 14 Jun 2019 05:34:07 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 8E068200E5A; Fri, 14 Jun 2019 11:34:04 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 148B6200E5C; Fri, 14 Jun 2019 11:33:59 +0200 (CEST) Received: from localhost.localdomain (mega.ap.freescale.net [10.192.208.232]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 441A6402E6; Fri, 14 Jun 2019 17:33:52 +0800 (SGT) From: Peter Chen To: balbi@kernel.org, shawnguo@kernel.org Cc: robh+dt@kernel.org, fabio.estevam@nxp.com, kernel@pengutronix.de, devicetree@vger.kernel.org, aisheng.dong@nxp.com, linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, chunfeng.yun@mediatek.com, Peter Chen Subject: [PATCH v4 2/8] usb: phy: phy-mxs-usb: add imx7ulp support Date: Fri, 14 Jun 2019 17:35:38 +0800 Message-Id: <20190614093544.11730-3-peter.chen@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190614093544.11730-1-peter.chen@nxp.com> References: <20190614093544.11730-1-peter.chen@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP At imx7ulp, the USB related analog register is located in PHY register region too, so we need to control PLL at PHY driver directly. Signed-off-by: Peter Chen --- drivers/usb/phy/phy-mxs-usb.c | 67 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c index 1b1bb0ad40c3..183467f74fe1 100644 --- a/drivers/usb/phy/phy-mxs-usb.c +++ b/drivers/usb/phy/phy-mxs-usb.c @@ -17,9 +17,11 @@ #include #include #include +#include #define DRIVER_NAME "mxs_phy" +/* Register Macro */ #define HW_USBPHY_PWD 0x00 #define HW_USBPHY_TX 0x10 #define HW_USBPHY_CTRL 0x30 @@ -37,6 +39,11 @@ #define GM_USBPHY_TX_TXCAL45DN(x) (((x) & 0xf) << 8) #define GM_USBPHY_TX_D_CAL(x) (((x) & 0xf) << 0) +/* imx7ulp */ +#define HW_USBPHY_PLL_SIC 0xa0 +#define HW_USBPHY_PLL_SIC_SET 0xa4 +#define HW_USBPHY_PLL_SIC_CLR 0xa8 + #define BM_USBPHY_CTRL_SFTRST BIT(31) #define BM_USBPHY_CTRL_CLKGATE BIT(30) #define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27) @@ -55,6 +62,12 @@ #define BM_USBPHY_IP_FIX (BIT(17) | BIT(18)) #define BM_USBPHY_DEBUG_CLKGATE BIT(30) +/* imx7ulp */ +#define BM_USBPHY_PLL_LOCK BIT(31) +#define BM_USBPHY_PLL_REG_ENABLE BIT(21) +#define BM_USBPHY_PLL_BYPASS BIT(16) +#define BM_USBPHY_PLL_POWER BIT(12) +#define BM_USBPHY_PLL_EN_USB_CLKS BIT(6) /* Anatop Registers */ #define ANADIG_ANA_MISC0 0x150 @@ -167,6 +180,9 @@ static const struct mxs_phy_data imx6ul_phy_data = { .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS, }; +static const struct mxs_phy_data imx7ulp_phy_data = { +}; + static const struct of_device_id mxs_phy_dt_ids[] = { { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, }, { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, }, @@ -174,6 +190,7 @@ static const struct of_device_id mxs_phy_dt_ids[] = { { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, }, { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, }, { .compatible = "fsl,imx6ul-usbphy", .data = &imx6ul_phy_data, }, + { .compatible = "fsl,imx7ulp-usbphy", .data = &imx7ulp_phy_data, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids); @@ -198,6 +215,11 @@ static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy) return mxs_phy->data == &imx6sl_phy_data; } +static inline bool is_imx7ulp_phy(struct mxs_phy *mxs_phy) +{ + return mxs_phy->data == &imx7ulp_phy_data; +} + /* * PHY needs some 32K cycles to switch from 32K clock to * bus (such as AHB/AXI, etc) clock. @@ -221,14 +243,49 @@ static void mxs_phy_tx_init(struct mxs_phy *mxs_phy) } } +static int mxs_phy_pll_enable(void __iomem *base, bool enable) +{ + int ret = 0; + + if (enable) { + u32 value; + + writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_SET); + writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_CLR); + writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_SET); + ret = readl_poll_timeout(base + HW_USBPHY_PLL_SIC, + value, (value & BM_USBPHY_PLL_LOCK) != 0, + 100, 10000); + if (ret) + return ret; + + writel(BM_USBPHY_PLL_EN_USB_CLKS, base + + HW_USBPHY_PLL_SIC_SET); + } else { + writel(BM_USBPHY_PLL_EN_USB_CLKS, base + + HW_USBPHY_PLL_SIC_CLR); + writel(BM_USBPHY_PLL_POWER, base + HW_USBPHY_PLL_SIC_CLR); + writel(BM_USBPHY_PLL_BYPASS, base + HW_USBPHY_PLL_SIC_SET); + writel(BM_USBPHY_PLL_REG_ENABLE, base + HW_USBPHY_PLL_SIC_CLR); + } + + return ret; +} + static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) { int ret; void __iomem *base = mxs_phy->phy.io_priv; + if (is_imx7ulp_phy(mxs_phy)) { + ret = mxs_phy_pll_enable(base, true); + if (ret) + return ret; + } + ret = stmp_reset_block(base + HW_USBPHY_CTRL); if (ret) - return ret; + goto disable_pll; /* Power up the PHY */ writel(0, base + HW_USBPHY_PWD); @@ -253,6 +310,11 @@ static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) mxs_phy_tx_init(mxs_phy); return 0; + +disable_pll: + if (is_imx7ulp_phy(mxs_phy)) + mxs_phy_pll_enable(base, false); + return ret; } /* Return true if the vbus is there */ @@ -374,6 +436,9 @@ static void mxs_phy_shutdown(struct usb_phy *phy) writel(BM_USBPHY_CTRL_CLKGATE, phy->io_priv + HW_USBPHY_CTRL_SET); + if (is_imx7ulp_phy(mxs_phy)) + mxs_phy_pll_enable(phy->io_priv, false); + clk_disable_unprepare(mxs_phy->clk); }