From patchwork Wed Sep 9 08:10:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JC Kuo X-Patchwork-Id: 11765057 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A2123138E for ; Wed, 9 Sep 2020 08:14:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7F42221D7A for ; Wed, 9 Sep 2020 08:14:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="Q5nGQsgh" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726708AbgIIIOU (ORCPT ); Wed, 9 Sep 2020 04:14:20 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:12006 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730079AbgIIIK4 (ORCPT ); Wed, 9 Sep 2020 04:10:56 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 09 Sep 2020 01:10:42 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 09 Sep 2020 01:10:55 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 09 Sep 2020 01:10:55 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 9 Sep 2020 08:10:54 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 9 Sep 2020 08:10:54 +0000 Received: from jckuo-lt.nvidia.com (Not Verified[10.19.100.126]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 09 Sep 2020 01:10:53 -0700 From: JC Kuo To: , , , , CC: , , , , , JC Kuo Subject: [PATCH v3 04/15] phy: tegra: xusb: tegra210: Do not reset UPHY PLL Date: Wed, 9 Sep 2020 16:10:30 +0800 Message-ID: <20200909081041.3190157-5-jckuo@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909081041.3190157-1-jckuo@nvidia.com> References: <20200909081041.3190157-1-jckuo@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1599639042; bh=WaPfusjwRvQ4H9NcenSUy4hF1eq88SicA4fEhsVWqjw=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=Q5nGQsgh0+bP9r7e12Y7HkPmLoHFhvJ0TCEXtXEP9PAOtr62M6mIUg0SUCAkZsPF2 GyvkuLuU9Ig3UKXvBAqnjmLzpQS0PeTdl1/oN9CH4xp1v0GHFyttumT3iyGx4bBYo4 yuNNWWvo8gZZyYEsxrAzPGr8l5e5xn/4mltXml5u0ADUy/r07spkECaEbCYou2v8z2 bvTf80sq29Zs55/iwl0JLWsv1Q2nLpGT0JY2XBSAWqSOawqyKzAJl/AlT1jZJXB2vC RNDHN8dwh4QnwsmC10MZsUQi2ucVB6v4Ys5yiol3uxvadYkMDxPcu2bWM4KWMjNHZe lGZzw6SRYmmmQ== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Once UPHY PLL hardware power sequencer is enabled, do not assert reset to PEX/SATA PLLs, otherwise UPHY PLL operation will be broken. This commit removes reset_control_assert(pcie->rst) and reset_control_assert(sata->rst) from PEX/SATA UPHY disable procedure. Signed-off-by: JC Kuo --- v3: new, was a part of "phy: tegra: xusb: Rearrange UPHY init on Tegra210" drivers/phy/tegra/xusb-tegra210.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c index f06e7bc7a51b..ef4bbcbed60b 100644 --- a/drivers/phy/tegra/xusb-tegra210.c +++ b/drivers/phy/tegra/xusb-tegra210.c @@ -504,7 +504,6 @@ static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl) if (--pcie->enable > 0) goto unlock; - reset_control_assert(pcie->rst); clk_disable_unprepare(pcie->pll); unlock: @@ -746,7 +745,6 @@ static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl) if (--sata->enable > 0) goto unlock; - reset_control_assert(sata->rst); clk_disable_unprepare(sata->pll); unlock: