From patchwork Thu Nov 19 08:53:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JC Kuo X-Patchwork-Id: 11916861 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C5EAC388F9 for ; Thu, 19 Nov 2020 08:55:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 477D524655 for ; Thu, 19 Nov 2020 08:55:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="K3jLRzde" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726546AbgKSIyT (ORCPT ); Thu, 19 Nov 2020 03:54:19 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:6176 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726375AbgKSIyT (ORCPT ); Thu, 19 Nov 2020 03:54:19 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Thu, 19 Nov 2020 00:54:22 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 19 Nov 2020 08:54:13 +0000 Received: from jckuo-lt.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 19 Nov 2020 08:54:11 +0000 From: JC Kuo To: , , , , CC: , , , , , JC Kuo , Thierry Reding Subject: [PATCH v5 02/16] clk: tegra: Don't enable PLLE HW sequencer at init Date: Thu, 19 Nov 2020 16:53:51 +0800 Message-ID: <20201119085405.556138-3-jckuo@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201119085405.556138-1-jckuo@nvidia.com> References: <20201119085405.556138-1-jckuo@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1605776063; bh=K6oHMTweFEihdXXYvcyusOm93g9OypwM/eKOtaoVQow=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=K3jLRzde6YkPB1QkfVKuVtU+NYIIWeuEjLNfqVDULzz1JHiMeehqzp++oc5gFG5gk 8dO/Ur6VwKhUO0X2qwKkweoffY7q8wIyMmAmc7Wl5/kohSgxvGS3Oxut/o/BSmwREZ lIllM+tYe0PF2sfKJlbWWb4D++A/jxNYjUgpjJsfee583dgVQz93qegLw3sDxuLz0z 9So5y+Y0g1PrOaOPk/JnFTJunGx8V7vAqiG4mM/MQrWwGPrHr2bEGI/y8K/ocFgwUj Jid1ap5eMjGtmxTbwj/4Xom2GVTj9OERrPLLmJcvm8bJBMzOsIIPWEvePWr6L+U9MS EG82LMqC3X2Mg== Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware power sequencers' output to enable/disable PLLE. PLLE hardware power sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers are enabled. Signed-off-by: JC Kuo Acked-by: Thierry Reding --- v5: no change v4: no change v3: no change drivers/clk/tegra/clk-pll.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c5cc0a2dac6f..0193cebe8c5a 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) pll_writel(val, PLLE_SS_CTRL, pll); udelay(1); - val = pll_readl_misc(pll); - val &= ~PLLE_MISC_IDDQ_SW_CTRL; - pll_writel_misc(val, pll); - - val = pll_readl(pll->params->aux_reg, pll); - val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE); - val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); - pll_writel(val, pll->params->aux_reg, pll); - udelay(1); - val |= PLLE_AUX_SEQ_ENABLE; - pll_writel(val, pll->params->aux_reg, pll); - out: if (pll->lock) spin_unlock_irqrestore(pll->lock, flags);