| Message ID | 20210108064148.26766-1-jckuo@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] xhci: tegra: Delay for disabling LFPS detector | expand |
On 8.1.2021 8.41, JC Kuo wrote: > Occasionally, we are seeing some SuperSpeed devices resumes right after > being directed to U3. This commits add 500us delay to ensure LFPS > detector is disabled before sending ACK to firmware. > > [ 16.099363] tegra-xusb 70090000.usb: entering ELPG > [ 16.104343] tegra-xusb 70090000.usb: 2-1 isn't suspended: 0x0c001203 > [ 16.114576] tegra-xusb 70090000.usb: not all ports suspended: -16 > [ 16.120789] tegra-xusb 70090000.usb: entering ELPG failed > > The register write passes through a few flop stages of 32KHz clock domain. > NVIDIA ASIC designer reviewed RTL and suggests 500us delay. > > Cc: stable@vger.kernel.org > Signed-off-by: JC Kuo <jckuo@nvidia.com> > --- > drivers/usb/host/xhci-tegra.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > changes in v2: > describes how 500us was determined in commit message > cc stable@vger.kernel.org > Thanks, added. -Mathias
diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c index 934be1686352..20cdc11f7dc6 100644 --- a/drivers/usb/host/xhci-tegra.c +++ b/drivers/usb/host/xhci-tegra.c @@ -623,6 +623,12 @@ static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, enable); if (err < 0) break; + + /* + * wait 500us for LFPS detector to be disabled before sending ACK + */ + if (!enable) + usleep_range(500, 1000); } if (err < 0) {
Occasionally, we are seeing some SuperSpeed devices resumes right after being directed to U3. This commits add 500us delay to ensure LFPS detector is disabled before sending ACK to firmware. [ 16.099363] tegra-xusb 70090000.usb: entering ELPG [ 16.104343] tegra-xusb 70090000.usb: 2-1 isn't suspended: 0x0c001203 [ 16.114576] tegra-xusb 70090000.usb: not all ports suspended: -16 [ 16.120789] tegra-xusb 70090000.usb: entering ELPG failed The register write passes through a few flop stages of 32KHz clock domain. NVIDIA ASIC designer reviewed RTL and suggests 500us delay. Cc: stable@vger.kernel.org Signed-off-by: JC Kuo <jckuo@nvidia.com> --- drivers/usb/host/xhci-tegra.c | 6 ++++++ 1 file changed, 6 insertions(+) changes in v2: describes how 500us was determined in commit message cc stable@vger.kernel.org