From patchwork Sat Jan 16 09:06:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunfeng Yun X-Patchwork-Id: 12024699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MIME_BASE64_TEXT,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1BE2C4332D for ; Sat, 16 Jan 2021 09:08:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D28DB23AC1 for ; Sat, 16 Jan 2021 09:08:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727187AbhAPJI0 (ORCPT ); Sat, 16 Jan 2021 04:08:26 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:46186 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726506AbhAPJH7 (ORCPT ); Sat, 16 Jan 2021 04:07:59 -0500 X-UUID: a74ab4bbbbb142cfbc7862f8f6dbfb7d-20210116 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VR5RTJ8obuOVwCZGur1zpK6Fre5HWsYtAU4oqij905Q=; b=GAVoH0nhQoeRIdpxR03iofk41yiKuR4PqLe5gG3hGyzhhVpzJ+3zpnnQ05wEL8GxESzBOc97t6F7J9Bz6Hp871fh42hvcOfEa9SoMLvBaASzXmbpe3IuiV0/42yki1yYmIlSL1Ws9I+XZFP4UA6tBCbTsNtLxX3LtJT0YAFyu6w=; X-UUID: a74ab4bbbbb142cfbc7862f8f6dbfb7d-20210116 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 930869144; Sat, 16 Jan 2021 17:07:07 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 16 Jan 2021 17:07:03 +0800 Received: from mtkslt301.mediatek.inc (10.21.14.114) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 16 Jan 2021 17:07:03 +0800 From: Chunfeng Yun To: Vinod Koul , Rob Herring , Greg Kroah-Hartman , Matthias Brugger CC: Chunfeng Yun , Kishon Vijay Abraham I , Chun-Kuang Hu , Philipp Zabel , Min Guo , , , , , Subject: [PATCH next 13/15] arm: dts: mt7629: harmonize node names and compatibles Date: Sat, 16 Jan 2021 17:06:54 +0800 Message-ID: <20210116090656.11752-13-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210116090656.11752-1-chunfeng.yun@mediatek.com> References: <20210116090656.11752-1-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 83740CD150C773CF618FC4FA73D09DAFF1321D15ABC9DA8D35617FCFD9397B312000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org This is used to fix dtbs_check warning Signed-off-by: Chunfeng Yun --- arch/arm/boot/dts/mt7629.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi index 5cbb3d244c75..874043f0490d 100644 --- a/arch/arm/boot/dts/mt7629.dtsi +++ b/arch/arm/boot/dts/mt7629.dtsi @@ -329,8 +329,9 @@ status = "disabled"; }; - u3phy0: usb-phy@1a0c4000 { - compatible = "mediatek,generic-tphy-v2"; + u3phy0: t-phy@1a0c4000 { + compatible = "mediatek,mt7629-tphy", + "mediatek,generic-tphy-v2"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1a0c4000 0xe00>; @@ -413,14 +414,15 @@ }; }; - pciephy1: pcie-phy@1a14a000 { - compatible = "mediatek,generic-tphy-v2"; + pciephy1: t-phy@1a14a000 { + compatible = "mediatek,mt7629-tphy", + "mediatek,generic-tphy-v2"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x1a14a000 0x1000>; status = "disabled"; - pcieport1: port1phy@0 { + pcieport1: pcie-phy@0 { reg = <0 0x1000>; clocks = <&clk20m>; clock-names = "ref";