From patchwork Wed Jan 20 07:34:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JC Kuo X-Patchwork-Id: 12031521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D36A8C433E6 for ; Wed, 20 Jan 2021 07:35:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9FEA623109 for ; Wed, 20 Jan 2021 07:35:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728958AbhATHf2 (ORCPT ); Wed, 20 Jan 2021 02:35:28 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:11182 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728750AbhATHfM (ORCPT ); Wed, 20 Jan 2021 02:35:12 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Tue, 19 Jan 2021 23:34:31 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 20 Jan 2021 07:34:28 +0000 Received: from jckuo-lt.nvidia.com (172.20.145.6) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Wed, 20 Jan 2021 07:34:25 +0000 From: JC Kuo To: , , , , , , CC: , , , , , , JC Kuo , Thierry Reding Subject: [PATCH v7 02/14] clk: tegra: Don't enable PLLE HW sequencer at init Date: Wed, 20 Jan 2021 15:34:02 +0800 Message-ID: <20210120073414.69208-3-jckuo@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210120073414.69208-1-jckuo@nvidia.com> References: <20210120073414.69208-1-jckuo@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1611128071; bh=1qxLHnWZ76Ctb3+TZ1NgN5gqXaf56lnLK3e6zE/Vu0w=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=Qx/HozEu1Fs4vXqLD1M9MlC+sQGVEUT8Ltd4PO6MQY/0EACh64MX+Hw0qyX1sYlzR D6gjGahxxmeaRAGaD4rUqlO3GsGeMPoshitO/H4dPIR9VC8Q+aJ22wpTFwEZ9e5J8X 0NCVmgr3drzu+L+0dDdR1+woCMTLp5+d8sTaBBZpmpm5fIZxDIZa7/4uS9lXvfR4i8 53b8v4Xzxxp41qthDwQIB7ttuLStOHK2kevVkSIpoyrv6p9sAzrYxDI3g3HGrcGI1q DoriKE6n6qJ1hhR2zs07QNSo2cg1C3NrRii/9qZkz1Ab1rtawUJ7PQI+isl6RCAT46 fDP0yOXRygcoQ== Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware power sequencers' output to enable/disable PLLE. PLLE hardware power sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers are enabled. Signed-off-by: JC Kuo Acked-by: Thierry Reding Acked-by: Stephen Boyd --- v7: no change v6: no change v5: no change v4: no change v3: no change drivers/clk/tegra/clk-pll.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c5cc0a2dac6f..0193cebe8c5a 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) pll_writel(val, PLLE_SS_CTRL, pll); udelay(1); - val = pll_readl_misc(pll); - val &= ~PLLE_MISC_IDDQ_SW_CTRL; - pll_writel_misc(val, pll); - - val = pll_readl(pll->params->aux_reg, pll); - val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE); - val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); - pll_writel(val, pll->params->aux_reg, pll); - udelay(1); - val |= PLLE_AUX_SEQ_ENABLE; - pll_writel(val, pll->params->aux_reg, pll); - out: if (pll->lock) spin_unlock_irqrestore(pll->lock, flags);