From patchwork Wed Feb 3 10:26:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunfeng Yun X-Patchwork-Id: 12063935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MIME_BASE64_TEXT,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3632BC43333 for ; Wed, 3 Feb 2021 10:28:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F1D5A64DF2 for ; Wed, 3 Feb 2021 10:28:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233912AbhBCK2Q (ORCPT ); Wed, 3 Feb 2021 05:28:16 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:15410 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233840AbhBCK1i (ORCPT ); Wed, 3 Feb 2021 05:27:38 -0500 X-UUID: 4f3509ed5a864599ae31313abd2c1798-20210203 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=oRQwwEBqC4tKIu7cXvamzV8CPVw7VRwU+JGP2zYTRyU=; b=VNzHi5FwcNFawbvb3kelq0+m02Q+mqSnGRZozUL+EB6RQ8tOSMoszXr89xzvmXC5EuBmGjCmsMMnf3PMbUvFVRO90qNJC/sT3KPNijEPQsb04Y3LI4ykrBeyK7mwXYJotMBao7c2AQFnyqg7HutZmU9nzENKb/HmO1zEKgNbqLo=; X-UUID: 4f3509ed5a864599ae31313abd2c1798-20210203 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1460794024; Wed, 03 Feb 2021 18:26:52 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 3 Feb 2021 18:26:46 +0800 Received: from mtkslt301.mediatek.inc (10.21.14.114) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 3 Feb 2021 18:26:46 +0800 From: Chunfeng Yun To: Rob Herring , Matthias Brugger , Mathias Nyman CC: Greg Kroah-Hartman , , , , , , Ikjoon Jang , Nicolas Boichat , Chunfeng Yun Subject: [RFC PATCH v2 1/3] dt-bindings: usb: mtk-xhci: add compatible for mt8195 Date: Wed, 3 Feb 2021 18:26:40 +0800 Message-ID: <20210203102642.7353-1-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: B45C9A23E638F617A8804501C1C14A4441E4A31D6616F8B7CF5DFAD9D9CF1FB82000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org There are 4 USB controllers on MT8195, the controllers (IP1~IP3, exclude IP0) have a wrong default SOF/ITP interval which is calculated from the frame counter clock 24Mhz by default, but in fact, the frame counter clock is 48Mhz, so we should set the accurate interval according to 48Mhz. Here add a new compatible for MT8195, it's also supported in driver. But the first controller (IP0) has no such issue, we prefer to use generic compatible, e.g. mt8192's compatible. Signed-off-by: Chunfeng Yun Acked-by: Rob Herring --- v2: no changes --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt index 42d8814f903a..02cba4212f7d 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt @@ -16,6 +16,7 @@ Required properties: "mediatek,mtk-xhci" compatible string, you need SoC specific ones in addition, one of: - "mediatek,mt8173-xhci" + - "mediatek,mt8195-xhci" - reg : specifies physical base address and size of the registers - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control - interrupts : interrupt used by the controller