diff mbox series

[1/1] usb: gadget: tegra-xudc: Fix control endpoint's definitions

Message ID 20220107091349.149798-1-waynec@nvidia.com (mailing list archive)
State Accepted
Commit 7bd42fb95eb4f98495ccadf467ad15124208ec49
Headers show
Series [1/1] usb: gadget: tegra-xudc: Fix control endpoint's definitions | expand

Commit Message

Wayne Chang Jan. 7, 2022, 9:13 a.m. UTC 
According to the Tegra Technical Reference Manual, the seq_num
field of control endpoint is not [31:24] but [31:27]. Bit 24
is reserved and bit 26 is splitxstate.

The change fixes the wrong control endpoint's definitions.

Signed-off-by: Wayne Chang <waynec@nvidia.com>
---
 drivers/usb/gadget/udc/tegra-xudc.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

Comments

Thierry Reding Feb. 25, 2022, 1:20 p.m. UTC | #1 
On Fri, Jan 07, 2022 at 05:13:49PM +0800, Wayne Chang wrote:
> According to the Tegra Technical Reference Manual, the seq_num
> field of control endpoint is not [31:24] but [31:27]. Bit 24
> is reserved and bit 26 is splitxstate.
> 
> The change fixes the wrong control endpoint's definitions.
> 
> Signed-off-by: Wayne Chang <waynec@nvidia.com>
> ---
>  drivers/usb/gadget/udc/tegra-xudc.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)

Again, what's the impact of this? Is this a critical bug fix that needs
to go into stable? Or is it cleanup? Perhaps add something along those
lines to the commit message to make it clearer to maintainers how they
need to deal with them.

Also, if this is a bugfix, make sure to Cc: stable@vger.kernel.org and
add a corresponding Fixes: line. Same for that earlier patch.

Thierry
diff mbox series

Patch

diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c
index 43f1b0d461c1..a8638feff46f 100644
--- a/drivers/usb/gadget/udc/tegra-xudc.c
+++ b/drivers/usb/gadget/udc/tegra-xudc.c
@@ -275,8 +275,10 @@  BUILD_EP_CONTEXT_RW(deq_hi, deq_hi, 0, 0xffffffff)
 BUILD_EP_CONTEXT_RW(avg_trb_len, tx_info, 0, 0xffff)
 BUILD_EP_CONTEXT_RW(max_esit_payload, tx_info, 16, 0xffff)
 BUILD_EP_CONTEXT_RW(edtla, rsvd[0], 0, 0xffffff)
-BUILD_EP_CONTEXT_RW(seq_num, rsvd[0], 24, 0xff)
+BUILD_EP_CONTEXT_RW(rsvd, rsvd[0], 24, 0x1)
 BUILD_EP_CONTEXT_RW(partial_td, rsvd[0], 25, 0x1)
+BUILD_EP_CONTEXT_RW(splitxstate, rsvd[0], 26, 0x1)
+BUILD_EP_CONTEXT_RW(seq_num, rsvd[0], 27, 0x1f)
 BUILD_EP_CONTEXT_RW(cerrcnt, rsvd[1], 18, 0x3)
 BUILD_EP_CONTEXT_RW(data_offset, rsvd[2], 0, 0x1ffff)
 BUILD_EP_CONTEXT_RW(numtrbs, rsvd[2], 22, 0x1f)
@@ -1557,6 +1559,9 @@  static int __tegra_xudc_ep_set_halt(struct tegra_xudc_ep *ep, bool halt)
 		ep_reload(xudc, ep->index);
 
 		ep_ctx_write_state(ep->context, EP_STATE_RUNNING);
+		ep_ctx_write_rsvd(ep->context, 0);
+		ep_ctx_write_partial_td(ep->context, 0);
+		ep_ctx_write_splitxstate(ep->context, 0);
 		ep_ctx_write_seq_num(ep->context, 0);
 
 		ep_reload(xudc, ep->index);
@@ -2812,7 +2817,10 @@  static void tegra_xudc_reset(struct tegra_xudc *xudc)
 	xudc->setup_seq_num = 0;
 	xudc->queued_setup_packet = false;
 
-	ep_ctx_write_seq_num(ep0->context, xudc->setup_seq_num);
+	ep_ctx_write_rsvd(ep0->context, 0);
+	ep_ctx_write_partial_td(ep0->context, 0);
+	ep_ctx_write_splitxstate(ep0->context, 0);
+	ep_ctx_write_seq_num(ep0->context, 0);
 
 	deq_ptr = trb_virt_to_phys(ep0, &ep0->transfer_ring[ep0->deq_ptr]);