diff mbox series

[v2,2/2] dt-bindings: usb: snps,dwc3: Add 'snps,global-regs-starting-offset' quirk

Message ID 20230412033006.10859-2-stanley_chang@realtek.com (mailing list archive)
State Superseded
Headers show
Series [v2,1/2] usb: dwc3: core: add support for remapping global register start address | expand

Commit Message

Stanley Chang[昌育德] April 12, 2023, 3:30 a.m. UTC
Add a new 'snps,global-regs-starting-offset' DT to dwc3 core to remap
the global register start address

The RTK DHC SoCs were designed the global register address offset at
0x8100. The default address is at DWC3_GLOBALS_REGS_START (0xc100).
Therefore, add the property of device-tree to adjust this start address.

Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
---
 Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Krzysztof Kozlowski April 12, 2023, 10:51 a.m. UTC | #1
On 12/04/2023 05:30, Stanley Chang wrote:
> Add a new 'snps,global-regs-starting-offset' DT to dwc3 core to remap
> the global register start address
> 
> The RTK DHC SoCs were designed the global register address offset at
> 0x8100. The default address is at DWC3_GLOBALS_REGS_START (0xc100).
> Therefore, add the property of device-tree to adjust this start address.
> 
> Signed-off-by: Stanley Chang <stanley_chang@realtek.com>

Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC.  It might happen, that command when run on an older
kernel, gives you outdated entries.  Therefore please be sure you base
your patches on recent Linux kernel.

Since you skipped lists used in automated check, that's
unfortunately: NAK


> ---
>  Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
Best regards,
Krzysztof
Stanley Chang[昌育德] April 12, 2023, 11:11 a.m. UTC | #2
> On 12/04/2023 05:30, Stanley Chang wrote:
> > Add a new 'snps,global-regs-starting-offset' DT to dwc3 core to remap
> > the global register start address
> >
> > The RTK DHC SoCs were designed the global register address offset at
> > 0x8100. The default address is at DWC3_GLOBALS_REGS_START (0xc100).
> > Therefore, add the property of device-tree to adjust this start address.
> >
> > Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
> 
> Please use scripts/get_maintainers.pl to get a list of necessary people and lists
> to CC.  It might happen, that command when run on an older kernel, gives
> you outdated entries.  Therefore please be sure you base your patches on
> recent Linux kernel.
> 
> Since you skipped lists used in automated check, that's
> unfortunately: NAK
> 
> 
> > ---
> >  Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 7 +++++++
> >  1 file changed, 7 insertions(+)
> Best regards,
> Krzysztof
> 
> 
CC more maintainers by using scripts/get_maintainers.pl

Thanks,
Stanley
Rob Herring April 12, 2023, 12:54 p.m. UTC | #3
On Tue, Apr 11, 2023 at 10:30 PM Stanley Chang
<stanley_chang@realtek.com> wrote:
>
> Add a new 'snps,global-regs-starting-offset' DT to dwc3 core to remap
> the global register start address
>
> The RTK DHC SoCs were designed the global register address offset at
> 0x8100. The default address is at DWC3_GLOBALS_REGS_START (0xc100).
> Therefore, add the property of device-tree to adjust this start address.
>
> Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
> ---
>  Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> index be36956af53b..5cbf3b7ded04 100644
> --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> @@ -359,6 +359,13 @@ properties:
>      items:
>        enum: [1, 4, 8, 16, 32, 64, 128, 256]
>
> +  snps,global-regs-starting-offset:
> +    description:
> +      value for remapping global register start address. For some dwc3
> +      controller, the dwc3 global register start address is not at
> +      default DWC3_GLOBALS_REGS_START (0xc100). This property is added to
> +      adjust the address.

We already have 'reg' or using a specific compatible to handle
differences. Use one of those, not a custom property. Generally,
properties should be used for things that vary per board, not fixed in
a given SoC.

Rob
Krzysztof Kozlowski April 12, 2023, 2:13 p.m. UTC | #4
On 12/04/2023 13:11, Stanley Chang[昌育德] wrote:
>> On 12/04/2023 05:30, Stanley Chang wrote:
>>> Add a new 'snps,global-regs-starting-offset' DT to dwc3 core to remap
>>> the global register start address
>>>
>>> The RTK DHC SoCs were designed the global register address offset at
>>> 0x8100. The default address is at DWC3_GLOBALS_REGS_START (0xc100).
>>> Therefore, add the property of device-tree to adjust this start address.
>>>
>>> Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
>>
>> Please use scripts/get_maintainers.pl to get a list of necessary people and lists
>> to CC.  It might happen, that command when run on an older kernel, gives
>> you outdated entries.  Therefore please be sure you base your patches on
>> recent Linux kernel.
>>
>> Since you skipped lists used in automated check, that's
>> unfortunately: NAK
>>
>>
>>> ---
>>>  Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 7 +++++++
>>>  1 file changed, 7 insertions(+)
>> Best regards,
>> Krzysztof
>>
>>
> CC more maintainers by using scripts/get_maintainers.pl

This does not work like this. It has to appear in the patchwork and be
tested by automated tools. Please resend.

Best regards,
Krzysztof
Stanley Chang[昌育德] April 13, 2023, 2:53 a.m. UTC | #5
> 
> On Tue, Apr 11, 2023 at 10:30 PM Stanley Chang
> <stanley_chang@realtek.com> wrote:
> >
> > Add a new 'snps,global-regs-starting-offset' DT to dwc3 core to remap
> > the global register start address
> >
> > The RTK DHC SoCs were designed the global register address offset at
> > 0x8100. The default address is at DWC3_GLOBALS_REGS_START (0xc100).
> > Therefore, add the property of device-tree to adjust this start address.
> >
> > Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
> > ---
> >  Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> > b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> > index be36956af53b..5cbf3b7ded04 100644
> > --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> > +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> > @@ -359,6 +359,13 @@ properties:
> >      items:
> >        enum: [1, 4, 8, 16, 32, 64, 128, 256]
> >
> > +  snps,global-regs-starting-offset:
> > +    description:
> > +      value for remapping global register start address. For some dwc3
> > +      controller, the dwc3 global register start address is not at
> > +      default DWC3_GLOBALS_REGS_START (0xc100). This property is
> added to
> > +      adjust the address.
> 
> We already have 'reg' or using a specific compatible to handle differences. Use
> one of those, not a custom property. Generally, properties should be used for
> things that vary per board, not fixed in a given SoC.
> 
> Rob
> 

The default offset is fixed by macro DWC3_GLOBALS_REGS_START, and it is not specified by reg.
The dwc3/core is a general driver for every dwc3 IP of SoCs,
and vendor's definition and compatible should specify on its parent.
If we add a specific compatible to dwc3/core driver, then it will break this rule.
Therefore, I use a property to adjust this offset. 
If no define this property, it will use default offset. So it will not affect other board.

Thanks,
Stanley
Krzysztof Kozlowski April 14, 2023, 9:08 a.m. UTC | #6
On 13/04/2023 04:53, Stanley Chang[昌育德] wrote:
> 
>>
>> On Tue, Apr 11, 2023 at 10:30 PM Stanley Chang
>> <stanley_chang@realtek.com> wrote:
>>>
>>> Add a new 'snps,global-regs-starting-offset' DT to dwc3 core to remap
>>> the global register start address
>>>
>>> The RTK DHC SoCs were designed the global register address offset at
>>> 0x8100. The default address is at DWC3_GLOBALS_REGS_START (0xc100).
>>> Therefore, add the property of device-tree to adjust this start address.
>>>
>>> Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
>>> ---
>>>  Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 7 +++++++
>>>  1 file changed, 7 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
>>> b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
>>> index be36956af53b..5cbf3b7ded04 100644
>>> --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
>>> +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
>>> @@ -359,6 +359,13 @@ properties:
>>>      items:
>>>        enum: [1, 4, 8, 16, 32, 64, 128, 256]
>>>
>>> +  snps,global-regs-starting-offset:
>>> +    description:
>>> +      value for remapping global register start address. For some dwc3
>>> +      controller, the dwc3 global register start address is not at
>>> +      default DWC3_GLOBALS_REGS_START (0xc100). This property is
>> added to
>>> +      adjust the address.
>>
>> We already have 'reg' or using a specific compatible to handle differences. Use
>> one of those, not a custom property. Generally, properties should be used for
>> things that vary per board, not fixed in a given SoC.
>>
>> Rob
>>
> 
> The default offset is fixed by macro DWC3_GLOBALS_REGS_START, and it is not specified by reg.

Are you saying that reg points to XHCI registers and the gap between
them and DWC3_GLOBALS_REGS_START is different on some implementations of
this IP?

> The dwc3/core is a general driver for every dwc3 IP of SoCs,
> and vendor's definition and compatible should specify on its parent.

Not entirely. It's how currently it is written, but not necessarily
correct representation. The parent is only glue part which for some
non-IP resources.

> If we add a specific compatible to dwc3/core driver, then it will break this rule.

What rule? The rule is to have specific compatibles, so now you are
breaking it.

> Therefore, I use a property to adjust this offset. 
> If no define this property, it will use default offset. So it will not affect other board.


Best regards,
Krzysztof
Stanley Chang[昌育德] April 14, 2023, 9:36 a.m. UTC | #7
> On 13/04/2023 04:53, Stanley Chang[昌育德] wrote:
> >
> >>
> >> On Tue, Apr 11, 2023 at 10:30 PM Stanley Chang
> >> <stanley_chang@realtek.com> wrote:
> >>>
> >>> Add a new 'snps,global-regs-starting-offset' DT to dwc3 core to
> >>> remap the global register start address
> >>>
> >>> The RTK DHC SoCs were designed the global register address offset at
> >>> 0x8100. The default address is at DWC3_GLOBALS_REGS_START (0xc100).
> >>> Therefore, add the property of device-tree to adjust this start address.
> >>>
> >>> Signed-off-by: Stanley Chang <stanley_chang@realtek.com>
> >>> ---
> >>>  Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 7 +++++++
> >>>  1 file changed, 7 insertions(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> >>> b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> >>> index be36956af53b..5cbf3b7ded04 100644
> >>> --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> >>> +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> >>> @@ -359,6 +359,13 @@ properties:
> >>>      items:
> >>>        enum: [1, 4, 8, 16, 32, 64, 128, 256]
> >>>
> >>> +  snps,global-regs-starting-offset:
> >>> +    description:
> >>> +      value for remapping global register start address. For some dwc3
> >>> +      controller, the dwc3 global register start address is not at
> >>> +      default DWC3_GLOBALS_REGS_START (0xc100). This property is
> >> added to
> >>> +      adjust the address.
> >>
> >> We already have 'reg' or using a specific compatible to handle
> >> differences. Use one of those, not a custom property. Generally,
> >> properties should be used for things that vary per board, not fixed in a given
> SoC.
> >>
> >> Rob
> >>
> >
> > The default offset is fixed by macro DWC3_GLOBALS_REGS_START, and it is
> not specified by reg.
> 
> Are you saying that reg points to XHCI registers and the gap between them and
> DWC3_GLOBALS_REGS_START is different on some implementations of this IP?

Yes.

> > The dwc3/core is a general driver for every dwc3 IP of SoCs, and
> > vendor's definition and compatible should specify on its parent.
> 
> Not entirely. It's how currently it is written, but not necessarily correct
> representation. The parent is only glue part which for some non-IP resources.

I agree. 
I think this offset belongs to the IP resource.
But it is fixed value on dwc3/core driver.
Therefore, I had to add this patch to adjust it.

> > If we add a specific compatible to dwc3/core driver, then it will break this
> rule.
> 
> What rule? The rule is to have specific compatibles, so now you are breaking it.
> 
I just don't want dwc3/core to look like a specific Realtek driver.
If I add compatible to our platform, then apply this offset.
For example,
@@ -2046,6 +2046,9 @@ static const struct of_device_id of_dwc3_match[] = {
        {
                .compatible = "synopsys,dwc3"
        },
+       {
+               .compatible = "realtek,dwc3"
+       },
        { },
 };

Why not use a property of the device tree to specify this offset?
It will be more general. Other vendor IPs can also use this option if desired.
For example,
@@ -123,7 +123,7 @@ port0_dwc3: dwc3_u2drd@98020000 {
                        compatible = "synopsys,dwc3", "syscon";
                        reg = <0x98020000 0x9000>;
                        interrupts = <0 95 4>;
+                       snps,global-regs-starting-offset = <0x8100>;
                        usb-phy = <&dwc3_u2drd_usb2phy>;
                        dr_mode = "host";
                        snps,dis_u2_susphy_quirk;
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
index be36956af53b..5cbf3b7ded04 100644
--- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
@@ -359,6 +359,13 @@  properties:
     items:
       enum: [1, 4, 8, 16, 32, 64, 128, 256]
 
+  snps,global-regs-starting-offset:
+    description:
+      value for remapping global register start address. For some dwc3
+      controller, the dwc3 global register start address is not at
+      default DWC3_GLOBALS_REGS_START (0xc100). This property is added to
+      adjust the address.
+
   port:
     $ref: /schemas/graph.yaml#/properties/port
     description: