diff mbox series

[v2,07/20] thunderbolt: Announce USB4 v2 connection manager support

Message ID 20230612082145.62218-8-mika.westerberg@linux.intel.com (mailing list archive)
State Accepted
Commit 14200a2631dd1f041201985e2a757d2d06ba2524
Headers show
Series thunderbolt: Initial USB4 v2 support | expand

Commit Message

Mika Westerberg June 12, 2023, 8:21 a.m. UTC
From: Gil Fine <gil.fine@intel.com>

Program the CMUV (Connection Manager USB4 Version) field for USB4 v2 and
v1 routers according to the spec.

Signed-off-by: Gil Fine <gil.fine@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
---
 drivers/thunderbolt/switch.c  | 8 ++++++--
 drivers/thunderbolt/tb_regs.h | 3 +++
 2 files changed, 9 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c
index a0451218af2a..ebe9559c8c79 100644
--- a/drivers/thunderbolt/switch.c
+++ b/drivers/thunderbolt/switch.c
@@ -2430,9 +2430,13 @@  int tb_switch_configure(struct tb_switch *sw)
 		/*
 		 * For USB4 devices, we need to program the CM version
 		 * accordingly so that it knows to expose all the
-		 * additional capabilities.
+		 * additional capabilities. Program it according to USB4
+		 * version to avoid changing existing (v1) routers behaviour.
 		 */
-		sw->config.cmuv = USB4_VERSION_1_0;
+		if (usb4_switch_version(sw) < 2)
+			sw->config.cmuv = ROUTER_CS_4_CMUV_V1;
+		else
+			sw->config.cmuv = ROUTER_CS_4_CMUV_V2;
 		sw->config.plug_events_delay = 0xa;
 
 		/* Enumerate the switch */
diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h
index 69455eaf6351..c8e40ef09903 100644
--- a/drivers/thunderbolt/tb_regs.h
+++ b/drivers/thunderbolt/tb_regs.h
@@ -195,6 +195,9 @@  struct tb_regs_switch_header {
 
 #define ROUTER_CS_1				0x01
 #define ROUTER_CS_4				0x04
+/* Used with the router cmuv field */
+#define ROUTER_CS_4_CMUV_V1			0x10
+#define ROUTER_CS_4_CMUV_V2			0x20
 #define ROUTER_CS_5				0x05
 #define ROUTER_CS_5_SLP				BIT(0)
 #define ROUTER_CS_5_WOP				BIT(1)