@@ -1309,6 +1309,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
&tx_thr_num_pkt_prd);
device_property_read_u8(dev, "snps,tx-max-burst-prd",
&tx_max_burst_prd);
+ device_property_read_u8(dev, "snps,num-trb-prefetch",
+ &dwc->num_trb_prefetch);
dwc->disable_scramble_quirk = device_property_read_bool(dev,
"snps,disable_scramble_quirk");
@@ -154,6 +154,8 @@
#define DWC3_DEPCMDPAR0 0x08
#define DWC3_DEPCMD 0x0c
+#define DWC32_DEPCMDPAR2_TRB_PREFETCH(n) (((n) & 0xff) << 24)
+
#define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
/* OTG Registers */
@@ -353,6 +355,7 @@
#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
/* Global HWPARAMS4 Register */
+#define DWC32_GHWPARAMS4_CACHE_TRBS(n) ((n) & 0x3f) /* DWC_usb32 only */
#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
#define DWC3_MAX_HIBER_SCRATCHBUFS 15
@@ -993,6 +996,7 @@ struct dwc3_scratchpad_array {
* @rx_max_burst_prd: max periodic ESS receive burst size
* @tx_thr_num_pkt_prd: periodic ESS transmit packet count
* @tx_max_burst_prd: max periodic ESS transmit burst size
+ * @num_trb_prefetch: number of TRBs to cache
* @hsphy_interface: "utmi" or "ulpi"
* @connected: true when we're connected to a host, false otherwise
* @delayed_status: true when gadget driver asks for delayed status
@@ -1187,6 +1191,7 @@ struct dwc3 {
u8 rx_max_burst_prd;
u8 tx_thr_num_pkt_prd;
u8 tx_max_burst_prd;
+ u8 num_trb_prefetch;
const char *hsphy_interface;
@@ -566,6 +566,15 @@ static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
if (action == DWC3_DEPCFG_ACTION_RESTORE)
params.param2 |= dep->saved_state;
+ if (dwc3_is_usb32(dwc) && dep->number > 1 && dwc->num_trb_prefetch) {
+ u32 hwparams4 = dwc->hwparams.hwparams4;
+ int trb_count_max = DWC32_GHWPARAMS4_CACHE_TRBS(hwparams4);
+ int trb_count;
+
+ trb_count = min_t(int, dwc->num_trb_prefetch, trb_count_max);
+ params.param2 |= DWC32_DEPCMDPAR2_TRB_PREFETCH(trb_count);
+ }
+
if (usb_endpoint_xfer_control(desc))
params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
DWC_usb32 has new feature that allows the controller to cache multiple TRBs for non-control endpoints. The number of TRB cache can be from 1 to DWC_USB32_CACHE_TRBS_PER_TRANSFER. By default, if the property is not set, then the controller will cache up to DWC_USB32_CACHE_TRBS_PER_TRANSFER number of TRBs. Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> --- drivers/usb/dwc3/core.c | 2 ++ drivers/usb/dwc3/core.h | 5 +++++ drivers/usb/dwc3/gadget.c | 9 +++++++++ 3 files changed, 16 insertions(+)