| Message ID | 1566999303-18795-1-git-send-email-Anson.Huang@nxp.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [V5,1/4] dt-bindings: watchdog: Add i.MX7ULP bindings | expand |
On Wed, Aug 28, 2019 at 09:35:00AM -0400, Anson Huang wrote: > Add the watchdog bindings for Freescale i.MX7ULP. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > Reviewed-by: Rob Herring <rohb@kernel.org> Missed this version. For the record: Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > Changes since V4: > - improve watchdog node name. > --- > .../bindings/watchdog/fsl-imx7ulp-wdt.txt | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > create mode 100644 Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt > > diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt > new file mode 100644 > index 0000000..f902508 > --- /dev/null > +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt > @@ -0,0 +1,22 @@ > +* Freescale i.MX7ULP Watchdog Timer (WDT) Controller > + > +Required properties: > +- compatible : Should be "fsl,imx7ulp-wdt" > +- reg : Should contain WDT registers location and length > +- interrupts : Should contain WDT interrupt > +- clocks: Should contain a phandle pointing to the gated peripheral clock. > + > +Optional properties: > +- timeout-sec : Contains the watchdog timeout in seconds > + > +Examples: > + > +wdog1: watchdog@403d0000 { > + compatible = "fsl,imx7ulp-wdt"; > + reg = <0x403d0000 0x10000>; > + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&pcc2 IMX7ULP_CLK_WDG1>; > + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; > + assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; > + timeout-sec = <40>; > +}; > -- > 2.7.4 >
diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt new file mode 100644 index 0000000..f902508 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt @@ -0,0 +1,22 @@ +* Freescale i.MX7ULP Watchdog Timer (WDT) Controller + +Required properties: +- compatible : Should be "fsl,imx7ulp-wdt" +- reg : Should contain WDT registers location and length +- interrupts : Should contain WDT interrupt +- clocks: Should contain a phandle pointing to the gated peripheral clock. + +Optional properties: +- timeout-sec : Contains the watchdog timeout in seconds + +Examples: + +wdog1: watchdog@403d0000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x403d0000 0x10000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc2 IMX7ULP_CLK_WDG1>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; + assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + timeout-sec = <40>; +};