diff mbox series

[6/7] arm64: dts: renesas: r8a774b1: Add PCIe device nodes

Message ID 1570178133-21532-7-git-send-email-fabrizio.castro@bp.renesas.com (mailing list archive)
State Not Applicable
Headers show
Series Add RZ/G2N MSIOF/RWDT/PCIEC support | expand

Commit Message

Fabrizio Castro Oct. 4, 2019, 8:35 a.m. UTC 
This patch adds PCIe{0,1} device nodes for R8A774B1 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 42 +++++++++++++++++++++++++++++--
 1 file changed, 40 insertions(+), 2 deletions(-)

Comments

Andrew Murray Oct. 4, 2019, 10:32 a.m. UTC | #1 
On Fri, Oct 04, 2019 at 09:35:32AM +0100, Fabrizio Castro wrote:
> This patch adds PCIe{0,1} device nodes for R8A774B1 SoC.
> 
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> ---

Reviewed-by: Andrew Murray <andrew.murray@arm.com>

>  arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 42 +++++++++++++++++++++++++++++--
>  1 file changed, 40 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
> index 3bd0b47..0163b284 100644
> --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
> @@ -1304,19 +1304,57 @@
>  		};
>  
>  		pciec0: pcie@fe000000 {
> +			compatible = "renesas,pcie-r8a774b1",
> +				     "renesas,pcie-rcar-gen3";
>  			reg = <0 0xfe000000 0 0x80000>;
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			bus-range = <0x00 0xff>;
> -			/* placeholder */
> +			device_type = "pci";
> +			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
> +				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
> +				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
> +				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
> +			/* Map all possible DDR as inbound ranges */
> +			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
> +			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 0>;
> +			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
> +			clock-names = "pcie", "pcie_bus";
> +			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
> +			resets = <&cpg 319>;
> +			status = "disabled";
>  		};
>  
>  		pciec1: pcie@ee800000 {
> +			compatible = "renesas,pcie-r8a774b1",
> +				     "renesas,pcie-rcar-gen3";
>  			reg = <0 0xee800000 0 0x80000>;
>  			#address-cells = <3>;
>  			#size-cells = <2>;
>  			bus-range = <0x00 0xff>;
> -			/* placeholder */
> +			device_type = "pci";
> +			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
> +				  0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
> +				  0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
> +				  0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
> +			/* Map all possible DDR as inbound ranges */
> +			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
> +			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0 0 0 0>;
> +			interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
> +			clock-names = "pcie", "pcie_bus";
> +			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
> +			resets = <&cpg 318>;
> +			status = "disabled";
>  		};
>  
>  		fdp1@fe940000 {
> -- 
> 2.7.4
>
Geert Uytterhoeven Oct. 9, 2019, 12:48 p.m. UTC | #2 
On Fri, Oct 4, 2019 at 10:36 AM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> This patch adds PCIe{0,1} device nodes for R8A774B1 SoC.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.5.

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 3bd0b47..0163b284 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -1304,19 +1304,57 @@ 
 		};
 
 		pciec0: pcie@fe000000 {
+			compatible = "renesas,pcie-r8a774b1",
+				     "renesas,pcie-rcar-gen3";
 			reg = <0 0xfe000000 0 0x80000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
-			/* placeholder */
+			device_type = "pci";
+			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+			/* Map all possible DDR as inbound ranges */
+			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+			clock-names = "pcie", "pcie_bus";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 319>;
+			status = "disabled";
 		};
 
 		pciec1: pcie@ee800000 {
+			compatible = "renesas,pcie-r8a774b1",
+				     "renesas,pcie-rcar-gen3";
 			reg = <0 0xee800000 0 0x80000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
-			/* placeholder */
+			device_type = "pci";
+			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
+				  0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
+				  0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
+				  0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
+			/* Map all possible DDR as inbound ranges */
+			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
+			clock-names = "pcie", "pcie_bus";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 318>;
+			status = "disabled";
 		};
 
 		fdp1@fe940000 {