From patchwork Tue Apr 28 13:08:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Shych X-Patchwork-Id: 11514513 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E6F6592C for ; Tue, 28 Apr 2020 13:08:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CF49D206D6 for ; Tue, 28 Apr 2020 13:08:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727073AbgD1NIf (ORCPT ); Tue, 28 Apr 2020 09:08:35 -0400 Received: from mail-il-dmz.mellanox.com ([193.47.165.129]:59331 "EHLO mellanox.co.il" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727025AbgD1NIf (ORCPT ); Tue, 28 Apr 2020 09:08:35 -0400 Received: from Internal Mail-Server by MTLPINE2 (envelope-from michaelsh@mellanox.com) with ESMTPS (AES256-SHA encrypted); 28 Apr 2020 16:08:30 +0300 Received: from r-build-lowlevel.mtr.labs.mlnx. (r-build-lowlevel.mtr.labs.mlnx [10.209.0.190]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 03SD8OAH026463; Tue, 28 Apr 2020 16:08:30 +0300 From: michaelsh@mellanox.com To: linux@roeck-us.net, wim@linux-watchdog.org, andy@infradead.org, dvhart@infradead.org Cc: linux-watchdog@vger.kernel.org, platform-driver-x86@vger.kernel.org, vadimp@mellanox.com, Michael Shych Subject: [PATCH v2 4/4] docs: watchdog: mlx-wdt: Add description of new watchdog type 3 Date: Tue, 28 Apr 2020 16:08:16 +0300 Message-Id: <20200428130816.582-5-michaelsh@mellanox.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20200428130816.582-1-michaelsh@mellanox.com> References: <20200428130816.582-1-michaelsh@mellanox.com> Sender: linux-watchdog-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org From: Michael Shych Add documentation with details of new type of Mellanox watchdog driver. Signed-off-by: Michael Shych Reviewed-by: Vadim Pasternak --- v1-v2: Add explanation about device registers order --- Documentation/watchdog/mlx-wdt.rst | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/watchdog/mlx-wdt.rst b/Documentation/watchdog/mlx-wdt.rst index bf5bafac47f0..241768b885a5 100644 --- a/Documentation/watchdog/mlx-wdt.rst +++ b/Documentation/watchdog/mlx-wdt.rst @@ -24,10 +24,19 @@ Type 2: Maximum timeout is 255 sec. Get time-left is supported. +Type 3: + Same as Type 2 with extended maximum timeout period. + Maximum timeout is 65535 sec. + Type 1 HW watchdog implementation exist in old systems and all new systems have type 2 HW watchdog. Two types of HW implementation have also different register map. +Type 3 HW watchdog implementation can exist on all Mellanox systems +with new programmer logic device. +It's differentiated by WD capability bit. +Old systems still have only one main watchdog. + Mellanox system can have 2 watchdogs: main and auxiliary. Main and auxiliary watchdog devices can be enabled together on the same system. @@ -54,3 +63,6 @@ The driver checks during initialization if the previous system reset was done by the watchdog. If yes, it makes a notification about this event. Access to HW registers is performed through a generic regmap interface. +Programmable logic device registers have little-endian order. +Watchdog type 3, 2-byte width fields should be converted from LE to CPU order +and vice versa.