From patchwork Mon Aug 26 15:25:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 13778036 Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D21719343D for ; Mon, 26 Aug 2024 15:25:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724685945; cv=none; b=S89XcHDO0fIDqz3DPde11XxdANx+fXQF8rj8iP/LmJ8vbfw9xTY6zB9cCCRRQOUdWXfvtGJ6F2Mh06y5b9uLPNxJHhq/cvjm1Jh0UYHoY3NOM9gKqq9h9D7bGcfB4nNdxSJta2dN1U6hiMv6d0xhBGG7Cb7Nw98OrionFcOE+7Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724685945; c=relaxed/simple; bh=k6LbIc2jJg3zKMILXb+jRoFBLVqs64NwoQfKeVOdnsc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=sSPk2Pvhyat7WE7ybdSiczZSh8ayf/Q+jQIii2prVJxHxPLwQLJD/XMDUabULDU1vIKbTa/1kIEK4+scMmabGEViAsAqDZ2mUgHol3XAgNZTvzILX2aE5R8GW4afZqa7lYIRFL0h7bRqXExqsPDjuX2c+ZGwOLRRNTJiCiBxkUM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=MU5S5ZY+; arc=none smtp.client-ip=209.85.208.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="MU5S5ZY+" Received: by mail-ed1-f42.google.com with SMTP id 4fb4d7f45d1cf-5bede548f7cso5289057a12.2 for ; Mon, 26 Aug 2024 08:25:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1724685941; x=1725290741; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yLj+gew1QgSzR+6tLXRsI26fMQn5qBjOlpoGoLMMWyA=; b=MU5S5ZY+SFUhNlvkXoRBeuz25j64xJaiAY/P4KMB6Vs0+Ow+Qq/4ZKbbj6ebU6a1In gSIqBJR+CHw2V9VaZpaiAttG5XcAobu8y9FxZelplr3uF+0cUIsPAELZKDHWGvoiE+C4 OX7V85u4OX4poZVUGIdY6litiHoUgrnKF9qgfHI8dzG71KQW1PwOqXPqaTAam9piNYWt kPX4CpBAocpccb7cIEnTnyI6RyWB6EM8eeJ4VWp9zkDThLtmFgxYEzkvHXFHESTCGYuo UDZsC0Ksimo4q3NGbXJz/VsATpa72Mnd7z22uAYVBdFIvt81XIfS9AhpXGaA56ISGTML r+sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1724685941; x=1725290741; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yLj+gew1QgSzR+6tLXRsI26fMQn5qBjOlpoGoLMMWyA=; b=gWV4afE76lqolUalpcUdEOI8X6pBfLdpfysIhNBBVe/rNvBvmFy83+KJHud+vkHUYG KWoy/XlV0m2oOZqWB0pVeWZZzld8+FJMd+z66bzEycyUg5ALncvjP3T+fJP3j7WGsvoo KG8t4T9v5xlAQwDDxPgL+qgSnNufZFBazXUchldkamBKG7dIcf89OzCOo3ajwHGU/Xuh ZwQ/0xPNSlhGMk05h7jVYp6uMGYNcqzyWRY44fMSVQ87wIVbMGrQhFTJ3qC4cG+ADpDf DHkoAYW37v1XgRgnKMyxjqnG6ENK3Cx6OgGCzROM1HaxJxzQ2+FjervJXwi4QSUVg/hL +YAA== X-Forwarded-Encrypted: i=1; AJvYcCUJ95rqHimpdNwTxzwsQRNLGEPVIynJjdkYXPFxHJDvCBzdiqzXhTqJPchcPh8kOxbP7I0X2Ar9qBAy0kvtCw==@vger.kernel.org X-Gm-Message-State: AOJu0Yx6P9QVd6r53ftUgm6HAlrN2ozL525EXe/AvO1XAONRKwUWKcJp H0lT7EU594W7yLxNgRG8rViaxAp/V2kpmGS8IJuw4ToKEAvuJB4zITwPPXApzh4= X-Google-Smtp-Source: AGHT+IG6E2yeW8GEmZyeekNoOsOqX1QNKEUe+k+7h7nml2dR/p7wfptf18JDvEbf2u/GJPPTtVzTGg== X-Received: by 2002:a17:907:eab:b0:a7d:e5b1:bf65 with SMTP id a640c23a62f3a-a86a5199167mr672448566b.21.1724685941137; Mon, 26 Aug 2024 08:25:41 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a868f437d5fsm683005866b.99.2024.08.26.08.25.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2024 08:25:40 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, wim@linux-watchdog.org, linux@roeck-us.net, ulf.hansson@linaro.org Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-pm@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 1/3] clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local ones Date: Mon, 26 Aug 2024 18:25:27 +0300 Message-Id: <20240826152529.2080248-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240826152529.2080248-1-claudiu.beznea.uj@bp.renesas.com> References: <20240826152529.2080248-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea For watchdog PM domain it is necessary to provide GENPD_FLAG_IRQ_SAFE flag to be able to power on the watchdog PM domain from atomic context. For this, adjust the current infrastructure to be able to provide GENPD_FLAG_* for individual PM domains. Signed-off-by: Claudiu Beznea --- drivers/clk/renesas/r9a08g045-cpg.c | 44 +++++++++++------------------ drivers/clk/renesas/rzg2l-cpg.c | 13 +++++---- drivers/clk/renesas/rzg2l-cpg.h | 10 ++----- 3 files changed, 28 insertions(+), 39 deletions(-) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index 213499fc8fb5..ec0672651fe0 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -9,6 +9,7 @@ #include #include #include +#include #include @@ -258,52 +259,41 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { /* Keep always-on domain on the first position for proper domains registration. */ DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON, DEF_REG_CONF(0, 0), - RZG2L_PD_F_ALWAYS_ON), + GENPD_FLAG_ALWAYS_ON), DEF_PD("gic", R9A08G045_PD_GIC, DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)), - RZG2L_PD_F_ALWAYS_ON), + GENPD_FLAG_ALWAYS_ON), DEF_PD("ia55", R9A08G045_PD_IA55, DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)), - RZG2L_PD_F_ALWAYS_ON), + GENPD_FLAG_ALWAYS_ON), DEF_PD("dmac", R9A08G045_PD_DMAC, DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)), - RZG2L_PD_F_ALWAYS_ON), + GENPD_FLAG_ALWAYS_ON), DEF_PD("wdt0", R9A08G045_PD_WDT0, - DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)), 0), DEF_PD("sdhi0", R9A08G045_PD_SDHI0, - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)), 0), DEF_PD("sdhi1", R9A08G045_PD_SDHI1, - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)), 0), DEF_PD("sdhi2", R9A08G045_PD_SDHI2, - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)), 0), DEF_PD("eth0", R9A08G045_PD_ETHER0, - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)), 0), DEF_PD("eth1", R9A08G045_PD_ETHER1, - DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)), 0), DEF_PD("i2c0", R9A08G045_PD_I2C0, - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)), 0), DEF_PD("i2c1", R9A08G045_PD_I2C1, - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)), 0), DEF_PD("i2c2", R9A08G045_PD_I2C2, - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)), 0), DEF_PD("i2c3", R9A08G045_PD_I2C3, - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)), 0), DEF_PD("scif0", R9A08G045_PD_SCIF0, - DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), - RZG2L_PD_F_NONE), + DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)), 0), DEF_PD("vbat", R9A08G045_PD_VBAT, DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), - RZG2L_PD_F_ALWAYS_ON), + GENPD_FLAG_ALWAYS_ON), }; const struct rzg2l_cpg_info r9a08g045_cpg_info = { diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 88bf39e8c79c..b97996e93042 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1680,11 +1680,13 @@ static int rzg2l_cpg_power_off(struct generic_pm_domain *domain) return 0; } -static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on) +static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, u32 genpd_flags, + bool always_on) { struct dev_power_governor *governor; - pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP; + pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP | + genpd_flags; pd->genpd.attach_dev = rzg2l_cpg_attach_dev; pd->genpd.detach_dev = rzg2l_cpg_detach_dev; if (always_on) { @@ -1712,7 +1714,7 @@ static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv) pd->genpd.name = np->name; pd->priv = priv; - ret = rzg2l_cpg_pd_setup(pd, true); + ret = rzg2l_cpg_pd_setup(pd, 0, true); if (ret) return ret; @@ -1777,7 +1779,8 @@ static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv) return ret; for (unsigned int i = 0; i < info->num_pm_domains; i++) { - bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON); + u32 genpd_flags = info->pm_domains[i].genpd_flags; + bool always_on = !!(genpd_flags & GENPD_FLAG_ALWAYS_ON); struct rzg2l_cpg_pd *pd; pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); @@ -1789,7 +1792,7 @@ static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv) pd->id = info->pm_domains[i].id; pd->priv = priv; - ret = rzg2l_cpg_pd_setup(pd, always_on); + ret = rzg2l_cpg_pd_setup(pd, genpd_flags, always_on); if (ret) return ret; diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index ecfe7e7ea8a1..881a89b5a710 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -270,14 +270,14 @@ struct rzg2l_cpg_pm_domain_conf { * struct rzg2l_cpg_pm_domain_init_data - PM domain init data * @name: PM domain name * @conf: PM domain configuration - * @flags: RZG2L PM domain flags (see RZG2L_PD_F_*) + * @genpd_flags: genpd flags (see GENPD_FLAG_*) * @id: PM domain ID (similar to the ones defined in * include/dt-bindings/clock/-cpg.h) */ struct rzg2l_cpg_pm_domain_init_data { const char * const name; struct rzg2l_cpg_pm_domain_conf conf; - u32 flags; + u32 genpd_flags; u16 id; }; @@ -288,13 +288,9 @@ struct rzg2l_cpg_pm_domain_init_data { .conf = { \ .mstop = (_mstop_conf), \ }, \ - .flags = (_flags), \ + .genpd_flags = (_flags), \ } -/* Power domain flags. */ -#define RZG2L_PD_F_ALWAYS_ON BIT(0) -#define RZG2L_PD_F_NONE (0) - /** * struct rzg2l_cpg_info - SoC-specific CPG Description *