From patchwork Mon Oct 7 06:34:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin-Ting Kuo X-Patchwork-Id: 13824119 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE575149C6A; Mon, 7 Oct 2024 06:34:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728282855; cv=none; b=p4vxD3NeI9Jl36oS6BjmDF6/HqIHGfZZGCOCs/1VMHCVNqk6qd04vvbS1fw/VnVEX8xAf6IiVil9JgJsYi27lfiR7gWICTnbnRWMiM2q9oqVh35O+DNeoOz2SzD2J1t4wpoyks2+RUurqLYoBhcUAGJN8pD+06VlmP/JxdF3r2w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728282855; c=relaxed/simple; bh=SfVok2QnDPH32Kmkcj3p1nt9RMkzDbWzinsZZpIrOOA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=k3Vu8tlKmX46KdTqSSJNyXcIr49wlRGpc2aL6CSLhtcCrvMSLS12UR6X49HJYUJViy45040InJuPSP3Z9nN5pNa7KMQUXGHZerPy/PTa0CNWAx3odxblxbChVYBE7PjBQH1Tz2OJhUtVD5pDDAJGEDDI2oASh/4yzXeBvX3pCZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Mon, 7 Oct 2024 14:34:08 +0800 Received: from aspeedtech.com (192.168.10.152) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 7 Oct 2024 14:34:08 +0800 From: Chin-Ting Kuo To: , , , , , , , , , , , , CC: , , , , Subject: [PATCH 2/4] ARM: dts: aspeed: Add WDT controller into alias field Date: Mon, 7 Oct 2024 14:34:06 +0800 Message-ID: <20241007063408.2360874-3-chin-ting_kuo@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241007063408.2360874-1-chin-ting_kuo@aspeedtech.com> References: <20241007063408.2360874-1-chin-ting_kuo@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add WDT controller into alias field. After that, WDT index, used to distinguish different WDT controllers in the driver, can be gotten by using of_alias_get_id dts API. Signed-off-by: Chin-Ting Kuo --- arch/arm/boot/dts/aspeed/aspeed-g4.dtsi | 2 ++ arch/arm/boot/dts/aspeed/aspeed-g5.dtsi | 3 +++ arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 4 ++++ 3 files changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi index 78c967812492..d8b4136d0ca0 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi @@ -29,6 +29,8 @@ aliases { serial3 = &uart4; serial4 = &uart5; serial5 = &vuart; + watchdog0 = &wdt1; + watchdog1 = &wdt2; }; cpus { diff --git a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi index 57a699a7c149..4dd220bca617 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi @@ -30,6 +30,9 @@ aliases { serial3 = &uart4; serial4 = &uart5; serial5 = &vuart; + watchdog0 = &wdt1; + watchdog1 = &wdt2; + watchdog2 = &wdt3; }; cpus { diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 8ed715bd53aa..c0a47c795fff 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -40,6 +40,10 @@ aliases { mdio1 = &mdio1; mdio2 = &mdio2; mdio3 = &mdio3; + watchdog0 = &wdt1; + watchdog1 = &wdt2; + watchdog2 = &wdt3; + watchdog3 = &wdt4; };