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Mon, 10 Feb 2025 10:49:27 -0800 (PST) Received: from prasmi.Home ([2a06:5906:61b:2d00:b833:1deb:a929:b461]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439452533ecsm22911525e9.0.2025.02.10.10.49.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Feb 2025 10:49:26 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wim Van Sebroeck , Guenter Roeck , Magnus Damm , Wolfram Sang Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 1/9] dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG Date: Mon, 10 Feb 2025 18:49:02 +0000 Message-ID: <20250210184910.161780-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250210184910.161780-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250210184910.161780-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset Select Registers (`CPG_ERRORRST_SELm`) and Error Reset Registers (`CPG_ERROR_RSTm`). The `CPG_ERRORRST_SELm` register must be configured to trigger a system reset in response to specific error conditions, while the `CPG_ERROR_RSTm` registers store the error interrupt factors that caused the system reset. These registers can be used by various IP blocks as needed. For example, in `CPG_ERRORRST_SEL2`, setting `BIT(1)` enables the WDT1 to issue a system reset upon a watchdog timer underflow. Similarly, `BIT(1)` in `CPG_ERROR_RST2` indicates whether the system reset was caused by a WDT1 underflow. This functionality allows the watchdog driver to configure the CPG_ERRORRST_SEL2 register and determine whether the system booted due to a `Power-on Reset` or a `Watchdog Reset`. Add the `syscon` compatible property to the RZ/V2H(P) and RZ/G3E CPG blocks, enabling drivers to access the `CPG_ERRORRST_SELm` and `CPG_ERROR_RSTm` registers as needed. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring (Arm) --- v3->v4 - Updated commit meessage v2->v3 - No change v1->v2 - No change --- .../devicetree/bindings/clock/renesas,rzv2h-cpg.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index c3fe76abd549..f42d79e73e70 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -17,9 +17,11 @@ description: properties: compatible: - enum: - - renesas,r9a09g047-cpg # RZ/G3E - - renesas,r9a09g057-cpg # RZ/V2H + items: + - enum: + - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g057-cpg # RZ/V2H + - const: syscon reg: maxItems: 1 @@ -73,7 +75,7 @@ additionalProperties: false examples: - | clock-controller@10420000 { - compatible = "renesas,r9a09g057-cpg"; + compatible = "renesas,r9a09g057-cpg", "syscon"; reg = <0x10420000 0x10000>; clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; clock-names = "audio_extal", "rtxin", "qextal";