| Message ID | 8d9b280065a663f2cf31db7b21a010aa781a0af1.1642525158.git.geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | arm64: renesas: Add R-Car S4-8 watchdog support on Spider | expand |
On Tue, Jan 18, 2022 at 06:09:01PM +0100, Geert Uytterhoeven wrote: > Add the module clock used by the RCLK Watchdog Timer (RWDT) on the > Renesas R-Car S4-8 (r8a779f0) SoC. Mark it as a critical clock, to > ensure uninterrupted watchdog operation. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
On Tue, Jan 18, 2022 at 06:09:01PM +0100, Geert Uytterhoeven wrote: > Add the module clock used by the RCLK Watchdog Timer (RWDT) on the > Renesas R-Car S4-8 (r8a779f0) SoC. Mark it as a critical clock, to > ensure uninterrupted watchdog operation. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Guenter Roeck <linux@roeck-us.net> > --- > drivers/clk/renesas/r8a779f0-cpg-mssr.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c > index 4100078406d67073..e48c5af7341454a7 100644 > --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c > @@ -121,6 +121,11 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { > DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER), > DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER), > DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), > + DEF_MOD("wdt", 907, R8A779F0_CLK_R), > +}; > + > +static const unsigned int r8a779f0_crit_mod_clks[] __initconst = { > + MOD_CLK_ID(907), /* WDT */ > }; > > /* > @@ -177,6 +182,10 @@ const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = { > .num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks), > .num_hw_mod_clks = 28 * 32, > > + /* Critical Module Clocks */ > + .crit_mod_clks = r8a779f0_crit_mod_clks, > + .num_crit_mod_clks = ARRAY_SIZE(r8a779f0_crit_mod_clks), > + > /* Callbacks */ > .init = r8a779f0_cpg_mssr_init, > .cpg_clk_register = rcar_gen4_cpg_clk_register,
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c index 4100078406d67073..e48c5af7341454a7 100644 --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c @@ -121,6 +121,11 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = { DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER), DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER), DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER), + DEF_MOD("wdt", 907, R8A779F0_CLK_R), +}; + +static const unsigned int r8a779f0_crit_mod_clks[] __initconst = { + MOD_CLK_ID(907), /* WDT */ }; /* @@ -177,6 +182,10 @@ const struct cpg_mssr_info r8a779f0_cpg_mssr_info __initconst = { .num_mod_clks = ARRAY_SIZE(r8a779f0_mod_clks), .num_hw_mod_clks = 28 * 32, + /* Critical Module Clocks */ + .crit_mod_clks = r8a779f0_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r8a779f0_crit_mod_clks), + /* Callbacks */ .init = r8a779f0_cpg_mssr_init, .cpg_clk_register = rcar_gen4_cpg_clk_register,
Add the module clock used by the RCLK Watchdog Timer (RWDT) on the Renesas R-Car S4-8 (r8a779f0) SoC. Mark it as a critical clock, to ensure uninterrupted watchdog operation. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- drivers/clk/renesas/r8a779f0-cpg-mssr.c | 9 +++++++++ 1 file changed, 9 insertions(+)