From patchwork Thu Aug 30 19:34:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gertjan van Wingerde X-Patchwork-Id: 1389371 Return-Path: X-Original-To: patchwork-linux-wireless@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id EF86D3FDF5 for ; Thu, 30 Aug 2012 19:40:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751275Ab2H3Tkn (ORCPT ); Thu, 30 Aug 2012 15:40:43 -0400 Received: from cpsmtpb-ews09.kpnxchange.com ([213.75.39.14]:4270 "EHLO cpsmtpb-ews09.kpnxchange.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750913Ab2H3Tkg (ORCPT ); Thu, 30 Aug 2012 15:40:36 -0400 Received: from cpsps-ews17.kpnxchange.com ([10.94.84.183]) by cpsmtpb-ews09.kpnxchange.com with Microsoft SMTPSVC(6.0.3790.4675); Thu, 30 Aug 2012 21:34:23 +0200 Received: from CPSMTPM-CMT104.kpnxchange.com ([195.121.3.20]) by cpsps-ews17.kpnxchange.com with Microsoft SMTPSVC(7.5.7601.17514); Thu, 30 Aug 2012 21:34:22 +0200 Received: from wingerd.gvw.nl ([86.87.118.224]) by CPSMTPM-CMT104.kpnxchange.com with Microsoft SMTPSVC(7.0.6002.18264); Thu, 30 Aug 2012 21:34:22 +0200 Received: by wingerd.gvw.nl (Postfix, from userid 1026) id D1412202BF3; Thu, 30 Aug 2012 21:34:21 +0200 (CEST) From: Gertjan van Wingerde To: , "John W. Linville" Cc: , Ivo van Doorn , Helmut Schaa , Gertjan van Wingerde , Subject: [PATCH 02/14] rt2x00: Align rt2400pci GPIOCSR definition with datasheet. Date: Thu, 30 Aug 2012 21:34:01 +0200 Message-Id: <1346355248-5331-3-git-send-email-gwingerde@gmail.com> X-Mailer: git-send-email 1.7.11.1 In-Reply-To: <1346355248-5331-2-git-send-email-gwingerde@gmail.com> References: <1346355248-5331-1-git-send-email-gwingerde@gmail.com> <1346355248-5331-2-git-send-email-gwingerde@gmail.com> X-OriginalArrivalTime: 30 Aug 2012 19:34:22.0384 (UTC) FILETIME=[74CD8B00:01CD86E6] Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org Datasheet indicates additional fields to set the GPIO direction. At the same time rename GPIOCSR_BIT to GPIOCSR_VAL to represent the actual meaning better. Signed-off-by: Gertjan van Wingerde Cc: diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c index 8b9dbd7..94f9aa2 100644 --- a/drivers/net/wireless/rt2x00/rt2400pci.c +++ b/drivers/net/wireless/rt2x00/rt2400pci.c @@ -205,7 +205,7 @@ static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) u32 reg; rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®); - return rt2x00_get_field32(reg, GPIOCSR_BIT0); + return rt2x00_get_field32(reg, GPIOCSR_VAL0); } #ifdef CONFIG_RT2X00_LIB_LEDS diff --git a/drivers/net/wireless/rt2x00/rt2400pci.h b/drivers/net/wireless/rt2x00/rt2400pci.h index d3a4a68..e4b07f0 100644 --- a/drivers/net/wireless/rt2x00/rt2400pci.h +++ b/drivers/net/wireless/rt2x00/rt2400pci.h @@ -660,16 +660,26 @@ /* * GPIOCSR: GPIO control register. + * GPIOCSR_VALx: Actual GPIO pin x value + * GPIOCSR_DIRx: GPIO direction: 0 = output; 1 = input */ #define GPIOCSR 0x0120 -#define GPIOCSR_BIT0 FIELD32(0x00000001) -#define GPIOCSR_BIT1 FIELD32(0x00000002) -#define GPIOCSR_BIT2 FIELD32(0x00000004) -#define GPIOCSR_BIT3 FIELD32(0x00000008) -#define GPIOCSR_BIT4 FIELD32(0x00000010) -#define GPIOCSR_BIT5 FIELD32(0x00000020) -#define GPIOCSR_BIT6 FIELD32(0x00000040) -#define GPIOCSR_BIT7 FIELD32(0x00000080) +#define GPIOCSR_VAL0 FIELD32(0x00000001) +#define GPIOCSR_VAL1 FIELD32(0x00000002) +#define GPIOCSR_VAL2 FIELD32(0x00000004) +#define GPIOCSR_VAL3 FIELD32(0x00000008) +#define GPIOCSR_VAL4 FIELD32(0x00000010) +#define GPIOCSR_VAL5 FIELD32(0x00000020) +#define GPIOCSR_VAL6 FIELD32(0x00000040) +#define GPIOCSR_VAL7 FIELD32(0x00000080) +#define GPIOCSR_DIR0 FIELD32(0x00000100) +#define GPIOCSR_DIR1 FIELD32(0x00000200) +#define GPIOCSR_DIR2 FIELD32(0x00000400) +#define GPIOCSR_DIR3 FIELD32(0x00000800) +#define GPIOCSR_DIR4 FIELD32(0x00001000) +#define GPIOCSR_DIR5 FIELD32(0x00002000) +#define GPIOCSR_DIR6 FIELD32(0x00004000) +#define GPIOCSR_DIR7 FIELD32(0x00008000) /* * BBPPCSR: BBP Pin control register.