From patchwork Sat Dec 7 02:17:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Kossifidis X-Patchwork-Id: 3304431 Return-Path: X-Original-To: patchwork-linux-wireless@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4E37DC0D4A for ; Sat, 7 Dec 2013 02:18:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 76E38203E6 for ; Sat, 7 Dec 2013 02:18:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AD4A8203DC for ; Sat, 7 Dec 2013 02:18:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754039Ab3LGCSy (ORCPT ); Fri, 6 Dec 2013 21:18:54 -0500 Received: from mail-we0-f182.google.com ([74.125.82.182]:59003 "EHLO mail-we0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753700Ab3LGCSx (ORCPT ); Fri, 6 Dec 2013 21:18:53 -0500 Received: by mail-we0-f182.google.com with SMTP id q59so1406175wes.41 for ; Fri, 06 Dec 2013 18:18:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=rJOO5W+2VfGaZLNZ0zzamA2Eq3fN7PEjmxZkuEG+SSY=; b=yEn4GixB0ZkXULWdYjvSNBblQITrSxWQ6ITSEgWADYTTzsU4BZILXCUKL+49WU3zf5 0GNK2CoKTTMQt/ovw0y4CZNF0/oCa0uslNwidgiDDfYDZVUPK2SJJ8ChNcItUsvH95Rv uCVHhipLrPkC81B9K+pvhMTEMgTF0O3baP4a5a1uiO1OQ7uPUV61TV1JL24GOgMnoifs +O3ziJcEOYCbSuyUq2n4tLOwsvO9domABkIvcCSOcmsk9WMnerew4j/MkGaHQks2qcRp ZPKaPFT5jqfJ/xdFweEgLeZfha0wT2eO6tCeOJBqSsfNwJXe6NNzEEenm5Lk+SjyvKhi 80eQ== X-Received: by 10.194.83.35 with SMTP id n3mr2989944wjy.80.1386382732294; Fri, 06 Dec 2013 18:18:52 -0800 (PST) Received: from localhost.localdomain (host-89-242-219-252.as13285.net. [89.242.219.252]) by mx.google.com with ESMTPSA id n6sm1318023wix.3.2013.12.06.18.18.51 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Dec 2013 18:18:51 -0800 (PST) From: Nick Kossifidis To: ath5k-devel@lists.ath5k.org, linux-wireless@vger.kernel.org Cc: linville@tuxdriver.com, mcgrof@gmail.com, jirislaby@gmail.com, klebanov@kit.edu, Nick Kossifidis Subject: [PATCH] ath5k: Reset Tx interrupt bits also on PISR Date: Sat, 7 Dec 2013 02:17:40 +0000 Message-Id: <1386382660-5040-1-git-send-email-mickflemm@gmail.com> X-Mailer: git-send-email 1.8.4.4 Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some cards don't update the PISR properly when all SISR bits for Tx interrupts are being cleared and as a result we get interrupt storm. Since we handle all tx queues all together (so we don't really use the SISR bits to do per-queue interrupt handling), we can manualy update PISR by doing a write-to-clear on its Tx interrupt bits. Signed-off-by: Nick Kossifidis --- drivers/net/wireless/ath/ath5k/dma.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/ath/ath5k/dma.c b/drivers/net/wireless/ath/ath5k/dma.c index ce86f15..84c01c5 100644 --- a/drivers/net/wireless/ath/ath5k/dma.c +++ b/drivers/net/wireless/ath/ath5k/dma.c @@ -616,7 +616,16 @@ ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask) * SISRs will also clear PISR so no need to worry here. */ - pisr_clear = pisr & ~AR5K_ISR_BITS_FROM_SISRS; + /* XXX: There seems to be an issue on some cards + * with tx interrupt flags not being updated + * on PISR despite that all Tx interrupt bits + * are cleared on SISRs. Since we handle all + * Tx queues all together it shouldn't be an + * issue if we clear Tx interrupt flags also + * on PISR to avoid that. + */ + pisr_clear = (pisr & ~AR5K_ISR_BITS_FROM_SISRS) | + (pisr & AR5K_INT_TX_ALL); /* * Write to clear them...