From patchwork Fri Jul 3 06:15:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vasanthakumar Thiagarajan X-Patchwork-Id: 6713001 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: X-Original-To: patchwork-linux-wireless@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 54912C05AC for ; Fri, 3 Jul 2015 06:16:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 75D7B204B5 for ; Fri, 3 Jul 2015 06:16:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4A7F620212 for ; Fri, 3 Jul 2015 06:16:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754623AbbGCGQI (ORCPT ); Fri, 3 Jul 2015 02:16:08 -0400 Received: from sabertooth01.qualcomm.com ([65.197.215.72]:60743 "EHLO sabertooth01.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754646AbbGCGQF (ORCPT ); Fri, 3 Jul 2015 02:16:05 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=qti.qualcomm.com; i=@qti.qualcomm.com; q=dns/txt; s=qcdkim; t=1435904165; x=1467440165; h=from:to:cc:subject:date:message-id:mime-version; bh=uiY2c5ivAOqBJQE5PizyzMjJLsofTu9EqpYrs+gHmaY=; b=OqRXs6+Xo+hSTJ4qnAz9LO5T7NamufQVgTBJI1Y9I2XOUZzKOflsFt1t mQm5JCtVcAfl2baKolnNlfLcmuq3Ud932JLDyTGJ5f8kX5A5N2gR9t9Mn wx4FZRU5yepIzmN5cQAqaaiRnuA15G+6H3OleTbg/ASetiOdsfpagq4o8 g=; X-IronPort-AV: E=McAfee;i="5700,7163,7850"; a="91961576" Received: from ironmsg04-r.qualcomm.com ([172.30.46.18]) by sabertooth01.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 02 Jul 2015 23:16:05 -0700 X-IronPort-AV: E=Sophos;i="5.15,398,1432623600"; d="scan'208";a="1005730055" Received: from nasanexm02f.na.qualcomm.com ([10.85.0.87]) by Ironmsg04-R.qualcomm.com with ESMTP/TLS/RC4-SHA; 02 Jul 2015 23:16:06 -0700 Received: from aphydexm01f.ap.qualcomm.com (10.252.127.15) by nasanexm02f.na.qualcomm.com (10.85.0.87) with Microsoft SMTP Server (TLS) id 15.0.1076.9; Thu, 2 Jul 2015 23:16:03 -0700 Received: from qcmail1.qualcomm.com (10.80.80.8) by aphydexm01f.ap.qualcomm.com (10.252.127.15) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Thu, 2 Jul 2015 23:15:53 -0700 Received: by qcmail1.qualcomm.com (sSMTP sendmail emulation); Fri, 03 Jul 2015 11:45:46 +0530 From: Vasanthakumar Thiagarajan To: CC: , Vasanthakumar Thiagarajan Subject: [PATCH] ath10k: Delay device access after cold reset Date: Fri, 3 Jul 2015 11:45:42 +0530 Message-ID: <1435904142-30295-1-git-send-email-vthiagar@qti.qualcomm.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: NASANEXM01B.na.qualcomm.com (10.85.0.82) To aphydexm01f.ap.qualcomm.com (10.252.127.15) Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP It is observed that during cold reset pcie access right after a write operation to SOC_GLOBAL_RESET_ADDRESS causes Data Bus Error and system hard lockup. The reason for bus error is that pcie needs some time to get back to stable state for any transaction during cold reset. Add delay of 20 msecs after write of SOC_GLOBAL_RESET_ADDRESS to fix this issue. Signed-off-by: Vasanthakumar Thiagarajan --- drivers/net/wireless/ath/ath10k/pci.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c index 1b4634a..130746b 100644 --- a/drivers/net/wireless/ath/ath10k/pci.c +++ b/drivers/net/wireless/ath/ath10k/pci.c @@ -2761,7 +2761,6 @@ static int ath10k_pci_wait_for_target_init(struct ath10k *ar) static int ath10k_pci_cold_reset(struct ath10k *ar) { - int i; u32 val; ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n"); @@ -2777,23 +2776,18 @@ static int ath10k_pci_cold_reset(struct ath10k *ar) val |= 1; ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); - for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) { - if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) & - RTC_STATE_COLD_RESET_MASK) - break; - msleep(1); - } + /* After writing into SOC_GLOBAL_RESET to put device into + * reset and pulling out of reset pcie may not be stable + * for any immediate pcie register access and cause bus error, + * add delay before any pcie access request to fix this issue. + */ + msleep(20); /* Pull Target, including PCIe, out of RESET. */ val &= ~1; ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); - for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) { - if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) & - RTC_STATE_COLD_RESET_MASK)) - break; - msleep(1); - } + msleep(20); ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");