From patchwork Tue Nov 23 19:02:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nick Kossifidis X-Patchwork-Id: 350281 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oANJ2Uu2007277 for ; Tue, 23 Nov 2010 19:02:30 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755479Ab0KWTC3 (ORCPT ); Tue, 23 Nov 2010 14:02:29 -0500 Received: from mail-ew0-f46.google.com ([209.85.215.46]:41988 "EHLO mail-ew0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754506Ab0KWTC2 (ORCPT ); Tue, 23 Nov 2010 14:02:28 -0500 Received: by ewy5 with SMTP id 5so2650325ewy.19 for ; Tue, 23 Nov 2010 11:02:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:date:from:to:cc:subject :message-id:mail-followup-to:mime-version:content-type :content-disposition:user-agent; bh=5rvKdXLjiCx3MKl2u6wbqoP5j2A22o5qLrm/E88epPA=; b=km65VNJAvpoSyj3AljbAm5K9M6L19NwGeUIkTFP31FUoa1EqoTBgUMzCJYvj+/WOLx 06+OM6tDC6K5EE3SyZtH6haSKfhwLmxjWFEsbh1Bt9Dma+Z8mmb7ilmU0JejUD59en4u yI+ebRFVI3cKXCLIFrn+YX9Lpsz7/K4MycBsc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=date:from:to:cc:subject:message-id:mail-followup-to:mime-version :content-type:content-disposition:user-agent; b=EMQqZpocY6TMsYpaISTw1grB6ecnMg0/eXqJ2I7uy15e2PLzDl9QCLvPo7arF6Fz1P TPoyLMzXrWj1TD91lFzonClBq+Kv4GEfOz3jBd1jFh8uqHdlHst4OpcoUuYNX2p6n4VQ a1M7j3yzJTI14/tXrA6YQ442/EQVo5epOlA2M= Received: by 10.213.113.210 with SMTP id b18mr2128513ebq.50.1290538947464; Tue, 23 Nov 2010 11:02:27 -0800 (PST) Received: from localhost ([139.91.73.37]) by mx.google.com with ESMTPS id v56sm6091054eeh.20.2010.11.23.11.02.21 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 23 Nov 2010 11:02:22 -0800 (PST) Date: Tue, 23 Nov 2010 21:02:20 +0200 From: Nick Kossifidis To: ath5k-devel@venema.h4ckr.net, linux-wireless@vger.kernel.org Cc: linville@tuxdriver.com, me@bobcopeland.com, mcgrof@gmail.com, jirislaby@gmail.com, nbd@openwrt.org, br1@einfach.org Subject: [PATCH 11/30] ath5k: Small cleanup on tweak_initvals Message-ID: <20101123190220.GK4303@makis.mantri> Mail-Followup-To: ath5k-devel@lists.ath5k.org, linux-wireless@vger.kernel.org, linville@tuxdriver.com, me@bobcopeland.com, mcgrof@gmail.com, jirislaby@gmail.com, nbd@openwrt.org, br1@einfach.org MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Tue, 23 Nov 2010 19:02:31 +0000 (UTC) diff --git a/drivers/net/wireless/ath/ath5k/reg.h b/drivers/net/wireless/ath/ath5k/reg.h index ca79ecd..4d61061 100644 --- a/drivers/net/wireless/ath/ath5k/reg.h +++ b/drivers/net/wireless/ath/ath5k/reg.h @@ -2058,6 +2058,7 @@ #define AR5K_PHY_SCAL 0x9878 #define AR5K_PHY_SCAL_32MHZ 0x0000000e +#define AR5K_PHY_SCAL_32MHZ_5311 0x00000008 #define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a #define AR5K_PHY_SCAL_32MHZ_HB63 0x00000032 diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c index a013bdf..f9457f4 100644 --- a/drivers/net/wireless/ath/ath5k/reset.c +++ b/drivers/net/wireless/ath/ath5k/reset.c @@ -730,24 +730,12 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah, ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL); } - if ((ah->ah_radio == AR5K_RF5112) && - (ah->ah_mac_srev < AR5K_SREV_AR5211)) { - u32 usec_reg; - /* 5311 has different tx/rx latency masks - * from 5211, since we deal 5311 the same - * as 5211 when setting initvals, shift - * values here to their proper locations */ - usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211); - ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 | - AR5K_USEC_32 | - AR5K_USEC_TX_LATENCY_5211 | - AR5K_REG_SM(29, - AR5K_USEC_RX_LATENCY_5210)), - AR5K_USEC_5211); + if (ah->ah_mac_srev < AR5K_SREV_AR5211) { /* Clear QCU/DCU clock gating register */ ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT); /* Set DAC/ADC delays */ - ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL); + ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311, + AR5K_PHY_SCAL); /* Enable PCU FIFO corruption ECO */ AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211, AR5K_DIAG_SW_ECO_ENABLE);