From patchwork Mon Jan 29 03:26:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ping-Ke Shih X-Patchwork-Id: 10188933 X-Patchwork-Delegate: kvalo@adurom.com Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7CC5D602C8 for ; Mon, 29 Jan 2018 03:27:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 735862871A for ; Mon, 29 Jan 2018 03:27:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 67BF52871C; Mon, 29 Jan 2018 03:27:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C42BC2465D for ; Mon, 29 Jan 2018 03:27:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751350AbeA2D1D (ORCPT ); Sun, 28 Jan 2018 22:27:03 -0500 Received: from rtits2.realtek.com ([211.75.126.72]:57303 "EHLO rtits2.realtek.com.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751197AbeA2D1B (ORCPT ); Sun, 28 Jan 2018 22:27:01 -0500 Authenticated-By: X-SpamFilter-By: BOX Solutions SpamTrap 5.62 with qID w0T3QpoN018652, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtitcas11.realtek.com.tw [172.21.6.12]) by rtits2.realtek.com.tw (8.15.2/2.57/5.78) with ESMTP id w0T3QpoN018652; Mon, 29 Jan 2018 11:26:51 +0800 Received: from RTITCASV01.realtek.com.tw (172.21.6.18) by RTITCAS11.realtek.com.tw (172.21.6.12) with Microsoft SMTP Server (TLS) id 14.3.351.0; Mon, 29 Jan 2018 11:26:50 +0800 Received: from localhost.localdomain (172.21.69.107) by RTITCASV01.realtek.com.tw (172.21.6.18) with Microsoft SMTP Server id 14.3.294.0; Mon, 29 Jan 2018 11:26:50 +0800 From: To: CC: , Subject: [PATCH v2 04/10] rtlwifi: Extend tx_power_by_rate_offset size for newer IC Date: Mon, 29 Jan 2018 11:26:35 +0800 Message-ID: <20180129032641.17841-5-pkshih@realtek.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180129032641.17841-1-pkshih@realtek.com> References: <20180129032641.17841-1-pkshih@realtek.com> MIME-Version: 1.0 X-Originating-IP: [172.21.69.107] Sender: linux-wireless-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ping-Ke Shih In older design, the TX power is grouped into rate section (smaller array size), but new design groups them into rate (larger array size). Thus, we extend the size for both cases, and add compile time assertion. Signed-off-by: Ping-Ke Shih Acked-by: Larry Finger --- drivers/net/wireless/realtek/rtlwifi/base.c | 2 ++ drivers/net/wireless/realtek/rtlwifi/wifi.h | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/realtek/rtlwifi/base.c b/drivers/net/wireless/realtek/rtlwifi/base.c index 92f99a303920..c000c85a3ded 100644 --- a/drivers/net/wireless/realtek/rtlwifi/base.c +++ b/drivers/net/wireless/realtek/rtlwifi/base.c @@ -2646,6 +2646,8 @@ EXPORT_SYMBOL_GPL(rtl_global_var); static int __init rtl_core_module_init(void) { + BUILD_BUG_ON(TX_PWR_BY_RATE_NUM_RATE < TX_PWR_BY_RATE_NUM_SECTION); + if (rtl_rate_control_register()) pr_err("rtl: Unable to register rtl_rc, use default RC !!\n"); diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h index be45420f34d3..5b29502a2864 100644 --- a/drivers/net/wireless/realtek/rtlwifi/wifi.h +++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h @@ -173,6 +173,7 @@ enum rtl8192c_h2c_cmd { #define TX_PWR_BY_RATE_NUM_BAND 2 #define TX_PWR_BY_RATE_NUM_RF 4 #define TX_PWR_BY_RATE_NUM_SECTION 12 +#define TX_PWR_BY_RATE_NUM_RATE 84 /* >= TX_PWR_BY_RATE_NUM_SECTION */ #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5 @@ -1285,7 +1286,7 @@ struct rtl_phy { u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND] [TX_PWR_BY_RATE_NUM_RF] [TX_PWR_BY_RATE_NUM_RF] - [TX_PWR_BY_RATE_NUM_SECTION]; + [TX_PWR_BY_RATE_NUM_RATE]; u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF] [TX_PWR_BY_RATE_NUM_RF] [MAX_BASE_NUM_IN_PHY_REG_PG_24G];