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Fri, 14 Feb 2020 11:52:24 +0000 From: To: CC: , , , , Subject: [PATCH 8/8] staging: wilc1000: define macros to replace magic number values Thread-Topic: [PATCH 8/8] staging: wilc1000: define macros to replace magic number values Thread-Index: AQHV4y04Pa/fqdvkgUei+QBjm2Y+9g== Date: Fri, 14 Feb 2020 11:52:23 +0000 Message-ID: <20200214172250.13026-9-ajay.kathat@microchip.com> References: <20200214172250.13026-1-ajay.kathat@microchip.com> In-Reply-To: <20200214172250.13026-1-ajay.kathat@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.17.1 x-originating-ip: [121.244.27.38] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 9307f65c-5d65-46a8-e9ee-08d7b1445b1a x-ms-traffictypediagnostic: BN6PR11MB1652: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:159; x-forefront-prvs: 03137AC81E x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(396003)(376002)(346002)(366004)(39850400004)(136003)(189003)(199004)(6506007)(2906002)(26005)(6512007)(2616005)(107886003)(6486002)(5660300002)(186003)(316002)(54906003)(4326008)(81156014)(81166006)(86362001)(64756008)(66476007)(66446008)(66556008)(8936002)(8676002)(30864003)(76116006)(91956017)(66946007)(478600001)(36756003)(6916009)(71200400001)(1076003);DIR:OUT;SFP:1101;SCL:1;SRVR:BN6PR11MB1652;H:BN6PR11MB3985.namprd11.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; 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Signed-off-by: Ajay Singh --- drivers/staging/wilc1000/sdio.c | 7 ++- drivers/staging/wilc1000/spi.c | 17 ++++--- drivers/staging/wilc1000/wlan.c | 83 +++++++++++++++++++-------------- drivers/staging/wilc1000/wlan.h | 35 ++++++++++++++ 4 files changed, 99 insertions(+), 43 deletions(-) diff --git a/drivers/staging/wilc1000/sdio.c b/drivers/staging/wilc1000/sdio.c index 0670c5956aef..2301e90c21ca 100644 --- a/drivers/staging/wilc1000/sdio.c +++ b/drivers/staging/wilc1000/sdio.c @@ -686,13 +686,16 @@ static int wilc_sdio_init(struct wilc *wilc, bool resume) * make sure can read back chip id correctly **/ if (!resume) { - ret = wilc_sdio_read_reg(wilc, 0x1000, &chipid); + int rev; + + ret = wilc_sdio_read_reg(wilc, WILC_CHIPID, &chipid); if (ret) { dev_err(&func->dev, "Fail cmd read chip id...\n"); return ret; } dev_err(&func->dev, "chipid (%08x)\n", chipid); - if ((chipid & 0xfff) > 0x2a0) + rev = FIELD_GET(WILC_CHIP_REV_FIELD, chipid); + if (rev > FIELD_GET(WILC_CHIP_REV_FIELD, WILC_1000_BASE_ID_2A)) sdio_priv->has_thrpt_enh3 = 1; else sdio_priv->has_thrpt_enh3 = 0; diff --git a/drivers/staging/wilc1000/spi.c b/drivers/staging/wilc1000/spi.c index 37be627e72ce..44f7d48851b5 100644 --- a/drivers/staging/wilc1000/spi.c +++ b/drivers/staging/wilc1000/spi.c @@ -683,7 +683,7 @@ static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data) u8 cmd = CMD_SINGLE_READ; u8 clockless = 0; - if (addr < 0x30) { + if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { /* Clockless register */ cmd = CMD_INTERNAL_READ; clockless = 1; @@ -760,7 +760,7 @@ static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data) u8 cmd = CMD_SINGLE_WRITE; u8 clockless = 0; - if (addr < 0x30) { + if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) { /* Clockless register */ cmd = CMD_INTERNAL_WRITE; clockless = 1; @@ -829,7 +829,7 @@ static int wilc_spi_init(struct wilc *wilc, bool resume) int ret; if (isinit) { - ret = wilc_spi_read_reg(wilc, 0x1000, &chipid); + ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); if (ret) dev_err(&spi->dev, "Fail cmd read chip id...\n"); @@ -881,7 +881,7 @@ static int wilc_spi_init(struct wilc *wilc, bool resume) /* * make sure can read back chip id correctly */ - ret = wilc_spi_read_reg(wilc, 0x1000, &chipid); + ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid); if (ret) { dev_err(&spi->dev, "Fail cmd read chip id...\n"); return ret; @@ -896,7 +896,8 @@ static int wilc_spi_read_size(struct wilc *wilc, u32 *size) { int ret; - ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE, size); + ret = spi_internal_read(wilc, + WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size); return ret; @@ -904,12 +905,14 @@ static int wilc_spi_read_size(struct wilc *wilc, u32 *size) static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status) { - return spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE, int_status); + return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, + int_status); } static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val) { - return spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE, val); + return spi_internal_write(wilc, WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, + val); } static int wilc_spi_sync_ext(struct wilc *wilc, int nint) diff --git a/drivers/staging/wilc1000/wlan.c b/drivers/staging/wilc1000/wlan.c index 31f424efe01d..f633c6b9f0a9 100644 --- a/drivers/staging/wilc1000/wlan.c +++ b/drivers/staging/wilc1000/wlan.c @@ -11,7 +11,7 @@ static inline bool is_wilc1000(u32 id) { - return (id & 0xfffff000) == 0x100000; + return (id & (~WILC_CHIP_REV_FIELD)) == WILC_1000_BASE_ID; } static inline void acquire_bus(struct wilc *wilc, enum bus_acquire acquire) @@ -393,10 +393,11 @@ void chip_allow_sleep(struct wilc *wilc) { u32 reg = 0; - wilc->hif_func->hif_read_reg(wilc, 0xf0, ®); + wilc->hif_func->hif_read_reg(wilc, WILC_SDIO_WAKEUP_REG, ®); - wilc->hif_func->hif_write_reg(wilc, 0xf0, reg & ~BIT(0)); - wilc->hif_func->hif_write_reg(wilc, 0xfa, 0); + wilc->hif_func->hif_write_reg(wilc, WILC_SDIO_WAKEUP_REG, + reg & ~WILC_SDIO_WAKEUP_BIT); + wilc->hif_func->hif_write_reg(wilc, WILC_SDIO_HOST_TO_FW_REG, 0); } EXPORT_SYMBOL_GPL(chip_allow_sleep); @@ -407,9 +408,11 @@ void chip_wakeup(struct wilc *wilc) if (wilc->io_type == WILC_HIF_SPI) { do { - h->hif_read_reg(wilc, 1, ®); - h->hif_write_reg(wilc, 1, reg | BIT(1)); - h->hif_write_reg(wilc, 1, reg & ~BIT(1)); + h->hif_read_reg(wilc, WILC_SPI_WAKEUP_REG, ®); + h->hif_write_reg(wilc, WILC_SPI_WAKEUP_REG, + reg | WILC_SPI_WAKEUP_BIT); + h->hif_write_reg(wilc, WILC_SPI_WAKEUP_REG, + reg & ~WILC_SPI_WAKEUP_BIT); do { usleep_range(2000, 2500); @@ -417,35 +420,40 @@ void chip_wakeup(struct wilc *wilc) } while (wilc_get_chipid(wilc, true) == 0); } while (wilc_get_chipid(wilc, true) == 0); } else if (wilc->io_type == WILC_HIF_SDIO) { - h->hif_write_reg(wilc, 0xfa, 1); + h->hif_write_reg(wilc, WILC_SDIO_HOST_TO_FW_REG, + WILC_SDIO_HOST_TO_FW_BIT); usleep_range(200, 400); - h->hif_read_reg(wilc, 0xf0, ®); + h->hif_read_reg(wilc, WILC_SDIO_WAKEUP_REG, ®); do { - h->hif_write_reg(wilc, 0xf0, reg | BIT(0)); - h->hif_read_reg(wilc, 0xf1, &clk_status_reg); + h->hif_write_reg(wilc, WILC_SDIO_WAKEUP_REG, + reg | WILC_SDIO_WAKEUP_BIT); + h->hif_read_reg(wilc, WILC_SDIO_CLK_STATUS_REG, + &clk_status_reg); - while ((clk_status_reg & 0x1) == 0) { + while (!(clk_status_reg & WILC_SDIO_CLK_STATUS_BIT)) { usleep_range(2000, 2500); - h->hif_read_reg(wilc, 0xf1, &clk_status_reg); + h->hif_read_reg(wilc, WILC_SDIO_CLK_STATUS_REG, + &clk_status_reg); } - if ((clk_status_reg & 0x1) == 0) { - h->hif_write_reg(wilc, 0xf0, reg & (~BIT(0))); + if (!(clk_status_reg & WILC_SDIO_CLK_STATUS_BIT)) { + h->hif_write_reg(wilc, WILC_SDIO_WAKEUP_REG, + reg & ~WILC_SDIO_WAKEUP_BIT); } - } while ((clk_status_reg & 0x1) == 0); + } while (!(clk_status_reg & WILC_SDIO_CLK_STATUS_BIT)); } if (wilc->chip_ps_state == WILC_CHIP_SLEEPING_MANUAL) { - if (wilc_get_chipid(wilc, false) < 0x1002b0) { + if (wilc_get_chipid(wilc, false) < WILC_1000_BASE_ID_2B) { u32 val32; - h->hif_read_reg(wilc, 0x1e1c, &val32); + h->hif_read_reg(wilc, WILC_REG_4_TO_1_RX, &val32); val32 |= BIT(6); - h->hif_write_reg(wilc, 0x1e1c, val32); + h->hif_write_reg(wilc, WILC_REG_4_TO_1_RX, val32); - h->hif_read_reg(wilc, 0x1e9c, &val32); + h->hif_read_reg(wilc, WILC_REG_4_TO_1_TX_BANK0, &val32); val32 |= BIT(6); - h->hif_write_reg(wilc, 0x1e9c, val32); + h->hif_write_reg(wilc, WILC_REG_4_TO_1_TX_BANK0, val32); } } wilc->chip_ps_state = WILC_CHIP_WAKEDUP; @@ -455,7 +463,7 @@ EXPORT_SYMBOL_GPL(chip_wakeup); void host_wakeup_notify(struct wilc *wilc) { acquire_bus(wilc, WILC_BUS_ACQUIRE_ONLY); - wilc->hif_func->hif_write_reg(wilc, 0x10b0, 1); + wilc->hif_func->hif_write_reg(wilc, WILC_CORTUS_INTERRUPT_2, 1); release_bus(wilc, WILC_BUS_RELEASE_ONLY); } EXPORT_SYMBOL_GPL(host_wakeup_notify); @@ -463,7 +471,7 @@ EXPORT_SYMBOL_GPL(host_wakeup_notify); void host_sleep_notify(struct wilc *wilc) { acquire_bus(wilc, WILC_BUS_ACQUIRE_ONLY); - wilc->hif_func->hif_write_reg(wilc, 0x10ac, 1); + wilc->hif_func->hif_write_reg(wilc, WILC_CORTUS_INTERRUPT_1, 1); release_bus(wilc, WILC_BUS_RELEASE_ONLY); } EXPORT_SYMBOL_GPL(host_sleep_notify); @@ -884,7 +892,7 @@ int wilc_wlan_start(struct wilc *wilc) wilc->hif_func->hif_sync_ext(wilc, NUM_INT_EXT); - ret = wilc->hif_func->hif_read_reg(wilc, 0x1000, &chipid); + ret = wilc->hif_func->hif_read_reg(wilc, WILC_CHIPID, &chipid); if (ret) { release_bus(wilc, WILC_BUS_RELEASE_ONLY); return ret; @@ -1125,18 +1133,24 @@ static int init_chip(struct net_device *dev) chipid = wilc_get_chipid(wilc, true); if ((chipid & 0xfff) != 0xa0) { - ret = wilc->hif_func->hif_read_reg(wilc, 0x1118, ®); + ret = wilc->hif_func->hif_read_reg(wilc, + WILC_CORTUS_RESET_MUX_SEL, + ®); if (ret) { netdev_err(dev, "fail read reg 0x1118\n"); goto release; } reg |= BIT(0); - ret = wilc->hif_func->hif_write_reg(wilc, 0x1118, reg); + ret = wilc->hif_func->hif_write_reg(wilc, + WILC_CORTUS_RESET_MUX_SEL, + reg); if (ret) { netdev_err(dev, "fail write reg 0x1118\n"); goto release; } - ret = wilc->hif_func->hif_write_reg(wilc, 0xc0000, 0x71); + ret = wilc->hif_func->hif_write_reg(wilc, + WILC_CORTUS_BOOT_REGISTER, + WILC_CORTUS_BOOT_FROM_IRAM); if (ret) { netdev_err(dev, "fail write reg 0xc0000\n"); goto release; @@ -1156,20 +1170,21 @@ u32 wilc_get_chipid(struct wilc *wilc, bool update) u32 rfrevid = 0; if (chipid == 0 || update) { - wilc->hif_func->hif_read_reg(wilc, 0x1000, &tempchipid); - wilc->hif_func->hif_read_reg(wilc, 0x13f4, &rfrevid); + wilc->hif_func->hif_read_reg(wilc, WILC_CHIPID, &tempchipid); + wilc->hif_func->hif_read_reg(wilc, WILC_RF_REVISION_ID, + &rfrevid); if (!is_wilc1000(tempchipid)) { chipid = 0; return chipid; } - if (tempchipid == 0x1002a0) { + if (tempchipid == WILC_1000_BASE_ID_2A) { /* 0x1002A0 */ if (rfrevid != 0x1) - tempchipid = 0x1002a1; - } else if (tempchipid == 0x1002b0) { + tempchipid = WILC_1000_BASE_ID_2A_REV1; + } else if (tempchipid == WILC_1000_BASE_ID_2B) { /* 0x1002B0 */ if (rfrevid == 0x4) - tempchipid = 0x1002b1; + tempchipid = WILC_1000_BASE_ID_2B_REV1; else if (rfrevid != 0x3) - tempchipid = 0x1002b2; + tempchipid = WILC_1000_BASE_ID_2B_REV2; } chipid = tempchipid; diff --git a/drivers/staging/wilc1000/wlan.h b/drivers/staging/wilc1000/wlan.h index ceec4801f18f..5999c5490ea5 100644 --- a/drivers/staging/wilc1000/wlan.h +++ b/drivers/staging/wilc1000/wlan.h @@ -66,6 +66,8 @@ #define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30) #define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40) +#define WILC_RF_REVISION_ID 0x13f4 + #define WILC_VMM_TBL_SIZE 64 #define WILC_VMM_TX_TBL_BASE 0x150400 #define WILC_VMM_RX_TBL_BASE 0x150500 @@ -89,10 +91,17 @@ #define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20) #define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24) #define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c) +#define WILC_SPI_INT_STATUS (WILC_SPI_REG_BASE + 0x40) +#define WILC_SPI_INT_CLEAR (WILC_SPI_REG_BASE + 0x44) + +#define WILC_SPI_WAKEUP_REG 0x1 +#define WILC_SPI_WAKEUP_BIT BIT(1) #define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - \ WILC_SPI_REG_BASE) +#define WILC_SPI_CLOCKLESS_ADDR_LIMIT 0x30 + /* Functions IO enables bits */ #define WILC_SDIO_CCCR_IO_EN_FUNC1 BIT(1) @@ -149,6 +158,32 @@ #define WILC_HAVE_DISABLE_WILC_UART BIT(7) #define WILC_HAVE_USE_IRQ_AS_HOST_WAKE BIT(8) +#define WILC_CORTUS_INTERRUPT_BASE 0x10A8 +#define WILC_CORTUS_INTERRUPT_1 (WILC_CORTUS_INTERRUPT_BASE + 0x4) +#define WILC_CORTUS_INTERRUPT_2 (WILC_CORTUS_INTERRUPT_BASE + 0x8) + +/* tx control register 1 to 4 for RX */ +#define WILC_REG_4_TO_1_RX 0x1e1c + +/* tx control register 1 to 4 for TX Bank_0 */ +#define WILC_REG_4_TO_1_TX_BANK0 0x1e9c + +#define WILC_CORTUS_RESET_MUX_SEL 0x1118 +#define WILC_CORTUS_BOOT_REGISTER 0xc0000 + +#define WILC_CORTUS_BOOT_FROM_IRAM 0x71 + +#define WILC_1000_BASE_ID 0x100000 + +#define WILC_1000_BASE_ID_2A 0x1002A0 +#define WILC_1000_BASE_ID_2A_REV1 (WILC_1000_BASE_ID_2A + 1) + +#define WILC_1000_BASE_ID_2B 0x1002B0 +#define WILC_1000_BASE_ID_2B_REV1 (WILC_1000_BASE_ID_2B + 1) +#define WILC_1000_BASE_ID_2B_REV2 (WILC_1000_BASE_ID_2B + 2) + +#define WILC_CHIP_REV_FIELD GENMASK(11, 0) + /******************************************** * * Wlan Defines