From patchwork Mon Mar 25 20:10:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pradeep Kumar Chitrapu X-Patchwork-Id: 13602846 X-Patchwork-Delegate: kvalo@adurom.com Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16AA9482EB for ; Mon, 25 Mar 2024 20:10:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711397458; cv=none; b=bJfYyHCvF1OpHYaI87xs7xIZgxz/uM+oeWuXBcQM88TR6LtFB+5eE9ur0UM4VyCaDjPrlBBSgupPYe/iWWjr3hLaJdK97t/F7WiI/hDDYjbazc1InfQGB6i8KO8P6Td8gzGYjj5roO5ZqewPf3DQ+PkuOIMPM1wnUdVt1/O/MsU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711397458; c=relaxed/simple; bh=UmCKuKHNN8Jz4Ku/RnqoX5FYUK34+noPHgmJxfIGG5Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cKZkWIzOtF+o6OWjI2Gwuca6/fO9Vav+uCVE5K6EM497dGJuTnXbLrBn6WsqJPPdIHLZCN37B6bZDZ6SDmnPxEdl0UEKfyvL7m4A1qt7blwP+8ZH70XRmReRa/RKZXW/kiwciKKOzW1/3UxpTuB9yKZk5yqk+hzRtlj9rsq4jrw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=R9Nmtey6; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="R9Nmtey6" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42PILgXR002892; Mon, 25 Mar 2024 20:10:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=VoAPYPhtd9xvIncO6Ju/ RbbEI5wAsH4VEwL1pyW/Eqw=; b=R9Nmtey6jwzBbf/vsWU4dYNXaJdQiIB9oo8c KYJgeC9mD79M8SlvK+YLU2Ca7QazKetBrqL+6hV4DptL0PG0PahJsVsVdSMBK81a 3JAbKr2xpnw9BPYd5zEtawHg8LIdRKUGgUTUhW1yt86M4snf9V8Oo347jE0zK9du CGOjjBF4EMsEP4yBiS3q56j0u4OoGphOtCp8SW8KAtLcxldNDxyA3IWCq1VZ7hVJ 597FjBr5ApXO8EQwpiSi6vefns6CF5KxhXhKXRE8eFjS6upFWacKGA0uh/FhKGla RSxGS5+BWKdtcEIp98KznwunNuoiBTlBuTFOaKrgBY5Y+3TZ9Q== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3x3626hjfv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Mar 2024 20:10:54 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42PKArZ4000541 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Mar 2024 20:10:53 GMT Received: from pradeepc2-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 25 Mar 2024 13:10:53 -0700 From: Pradeep Kumar Chitrapu To: CC: , Pradeep Kumar Chitrapu Subject: [PATCH 10/10] wifi: ath12k: add extended NSS bandwidth support for 160 MHz Date: Mon, 25 Mar 2024 13:10:31 -0700 Message-ID: <20240325201031.10837-11-quic_pradeepc@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240325201031.10837-1-quic_pradeepc@quicinc.com> References: <20240325201031.10837-1-quic_pradeepc@quicinc.com> Precedence: bulk X-Mailing-List: linux-wireless@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: VxFZ46S1v8DaAsgsyYmEhr8e5yFcZzwM X-Proofpoint-GUID: VxFZ46S1v8DaAsgsyYmEhr8e5yFcZzwM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-25_19,2024-03-21_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 phishscore=0 adultscore=0 clxscore=1015 malwarescore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403250123 Currently rx and tx MCS map for 160 MHz under HE capabilities are not updating properly, when 160 MHz is configured with NSS lesser than max NSS support. Fix this by utilizing nss_ratio_enabled and nss_ratio_info fields sent by firmware in service ready event. However, if firmware advertises EXT NSS BW support in VHT caps as 1(1x2) and when nss_ratio_info indicates 1:1, reset the EXT NSS BW Support in VHT caps to 0 which indicates 1x1. This is to avoid incorrectly chosing 1:2 NSS ratio when using the default VHT caps advertised by firmware. Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.0.1-00029-QCAHKSWPL_SILICONZ-1 Signed-off-by: Pradeep Kumar Chitrapu --- drivers/net/wireless/ath/ath12k/mac.c | 33 ++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/mac.c b/drivers/net/wireless/ath/ath12k/mac.c index 92b597697603..a5044b734868 100644 --- a/drivers/net/wireless/ath/ath12k/mac.c +++ b/drivers/net/wireless/ath/ath12k/mac.c @@ -2103,8 +2103,10 @@ static void ath12k_peer_assoc_h_he(struct ath12k *ar, arg->peer_nss = min(sta->deflink.rx_nss, max_nss); if (arg->peer_phymode == MODE_11AX_HE160) { - tx_nss = ath12k_get_nss_160mhz(ar, max_nss); + tx_nss = ath12k_get_nss_160mhz(ar, ar->num_tx_chains); rx_nss = min(arg->peer_nss, tx_nss); + + arg->peer_nss = min(sta->deflink.rx_nss, ar->num_rx_chains); arg->peer_bw_rxnss_override = ATH12K_BW_NSS_MAP_ENABLE; if (!rx_nss) { @@ -4993,6 +4995,12 @@ ath12k_create_vht_cap(struct ath12k *ar, u32 rate_cap_tx_chainmask, vht_cap.vht_mcs.rx_mcs_map = cpu_to_le16(rxmcs_map); vht_cap.vht_mcs.tx_mcs_map = cpu_to_le16(txmcs_map); + /* Check if the HW supports 1:1 NSS ratio and reset + * EXT NSS BW Support field to 0 to indicate 1:1 ratio + */ + if (ar->pdev->cap.nss_ratio_info == WMI_NSS_RATIO_1_NSS) + vht_cap.cap &= ~IEEE80211_VHT_CAP_EXT_NSS_BW_MASK; + return vht_cap; } @@ -5175,11 +5183,12 @@ static void ath12k_mac_set_hemcsmap(struct ath12k *ar, struct ieee80211_sta_he_cap *he_cap) { struct ieee80211_he_mcs_nss_supp *mcs_nss = &he_cap->he_mcs_nss_supp; - u16 txmcs_map, rxmcs_map; + u8 maxtxnss_160 = ath12k_get_nss_160mhz(ar, ar->num_tx_chains); + u8 maxrxnss_160 = ath12k_get_nss_160mhz(ar, ar->num_rx_chains); + u16 txmcs_map_160 = 0, rxmcs_map_160 = 0; + u16 txmcs_map = 0, rxmcs_map = 0; u32 i; - rxmcs_map = 0; - txmcs_map = 0; for (i = 0; i < 8; i++) { if (i < ar->num_tx_chains && (ar->cfg_tx_chainmask >> cap->tx_chain_mask_shift) & BIT(i)) @@ -5192,12 +5201,24 @@ static void ath12k_mac_set_hemcsmap(struct ath12k *ar, rxmcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); else rxmcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); + + if (i < maxtxnss_160 && + (ar->cfg_tx_chainmask >> cap->tx_chain_mask_shift) & BIT(i)) + txmcs_map_160 |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); + else + txmcs_map_160 |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); + + if (i < maxrxnss_160 && + (ar->cfg_tx_chainmask >> cap->tx_chain_mask_shift) & BIT(i)) + rxmcs_map_160 |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); + else + rxmcs_map_160 |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); } mcs_nss->rx_mcs_80 = cpu_to_le16(rxmcs_map & 0xffff); mcs_nss->tx_mcs_80 = cpu_to_le16(txmcs_map & 0xffff); - mcs_nss->rx_mcs_160 = cpu_to_le16(rxmcs_map & 0xffff); - mcs_nss->tx_mcs_160 = cpu_to_le16(txmcs_map & 0xffff); + mcs_nss->rx_mcs_160 = cpu_to_le16(rxmcs_map_160 & 0xffff); + mcs_nss->tx_mcs_160 = cpu_to_le16(txmcs_map_160 & 0xffff); } static void ath12k_mac_copy_he_cap(struct ath12k *ar,