From patchwork Tue Oct 22 11:08:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kang Yang X-Patchwork-Id: 13845603 X-Patchwork-Delegate: quic_jjohnson@quicinc.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94BC219C578 for ; Tue, 22 Oct 2024 11:09:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729595346; cv=none; b=JHuvcx1D+eQoVYl9zmFapUXTKaUv2NLzlPEZLrVG0R12r7JHfD6bamdh8+F93fiQQS27uXdfXHkwQuWdRt7ZsAXOYB+Kq5C/TyndeI8hydQHjdYehKVppakT4rOQwg2lpKal5Adoax3QHfwAi98dkEDqk+ujOhlB9qXRjKtpIVw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729595346; c=relaxed/simple; bh=ndyMJihkdEQ9aQJ0plZop3lWbAuKQuGp/pltDdsUENE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=O5GifQzgjtz7rMpepwTzZ49eqLIngUHNdvUEQzSzwycr7iMVLNWhCXh+bAZo082Az4FIVkTNbt1eTcaOKp+GUXTH2X0SkJMvntQyWkNQnaa6tW2AbaWPp6KReognXtWcdDB7PP/gmV2KTh98zcAXSGm1bDuE/L1Gc6nl33zyhos= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=UAjWwAEV; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="UAjWwAEV" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49M6l3rQ009622; Tue, 22 Oct 2024 11:09:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= lX6Tiuudtz4TB40toBVkIAo/QSWRw5z0MJCRHJxGUpI=; b=UAjWwAEVVy44Dgvd 7Kz/HtbsRKygz2epUm7gUeF0z2UQsNHOKalMO5c7li/Eb377WWQXO20yLSw58qic JVhHX4rHBZXI4C/D45fjFDQrNV0JUXaN46+IuTWtOCqSY9wnMxzDR44YhIqf1grz CMb8MQzx1l9R3VboE7q/OpNQhtndKgt1O5fQcbB9jlLmrXV6Z3NjqULblKwVVGuu Wkv4/wYBBAIFBN6CcorySQmpUOcSrRbMbIqMSIQ9ZTARRQlXBZtZHrAW/Vdli+B0 n892aEsIbsBCJc1cMb77Unk2tGZetBwI4xod1akAQFMmneOXFxeXIk3vGphVM850 NauZ8w== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42dkbt4ac9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Oct 2024 11:09:01 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49MB90Vf027459 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 22 Oct 2024 11:09:00 GMT Received: from kangyang.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 22 Oct 2024 04:08:58 -0700 From: Kang Yang To: CC: , Subject: [PATCH v6 5/8] wifi: ath12k: fix struct hal_rx_mpdu_start Date: Tue, 22 Oct 2024 19:08:28 +0800 Message-ID: <20241022110831.974-6-quic_kangyang@quicinc.com> X-Mailer: git-send-email 2.34.1.windows.1 In-Reply-To: <20241022110831.974-1-quic_kangyang@quicinc.com> References: <20241022110831.974-1-quic_kangyang@quicinc.com> Precedence: bulk X-Mailing-List: linux-wireless@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: wkGi_IYh5ZUes_7PdAuQr-jWlYV4b-gj X-Proofpoint-GUID: wkGi_IYh5ZUes_7PdAuQr-jWlYV4b-gj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=664 clxscore=1015 suspectscore=0 phishscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410220071 Current struct hal_rx_mpdu_start in hal_rx.h is not matched with hardware descriptor definition. This hardware descriptor definition is determined by hardware. Host shall follow it. So update struct hal_rx_mpdu_start and related code. Both QCN9274 and WCN7850 need this modification. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3 Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0-03427-QCAHMTSWPL_V1.0_V2.0_SILICONZ-1.15378.4 Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.1.1-00210-QCAHKSWPL_SILICONZ-1 Signed-off-by: Kang Yang --- drivers/net/wireless/ath/ath12k/hal_rx.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/hal_rx.h b/drivers/net/wireless/ath/ath12k/hal_rx.h index c69df852ae69..2de7b0eba9f2 100644 --- a/drivers/net/wireless/ath/ath12k/hal_rx.h +++ b/drivers/net/wireless/ath/ath12k/hal_rx.h @@ -452,15 +452,16 @@ struct hal_rx_phyrx_rssi_legacy_info { __le32 rsvd1; } __packed; -#define HAL_RX_MPDU_START_INFO0_PPDU_ID GENMASK(31, 16) -#define HAL_RX_MPDU_START_INFO1_PEERID GENMASK(31, 16) -#define HAL_RX_MPDU_START_INFO2_MPDU_LEN GENMASK(13, 0) +#define HAL_RX_MPDU_START_INFO0_PPDU_ID GENMASK(31, 16) +#define HAL_RX_MPDU_START_INFO1_PEERID GENMASK(31, 16) +#define HAL_RX_MPDU_START_INFO2_MPDU_LEN GENMASK(13, 0) struct hal_rx_mpdu_start { + __le32 rsvd0[9]; __le32 info0; __le32 info1; - __le32 rsvd1[11]; + __le32 rsvd1[2]; __le32 info2; - __le32 rsvd2[9]; + __le32 rsvd2[16]; } __packed; #define HAL_RX_PPDU_END_DURATION GENMASK(23, 0)