| Message ID | 20250313-mhi_bw_up-v2-6-869ca32170bf@oss.qualcomm.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Johannes Berg |
| Headers | show |
| Series | bus: mhi: host: Add support for mhi bus bw | expand |
On Thu, Mar 13, 2025 at 05:10:13PM +0530, Krishna Chaitanya Chundru wrote: > From: Vivek Pernamitta <quic_vpernami@quicinc.com> > > As per MHI spec sec 6.6, MHI has capability registers which are located > after the ERDB array. The location of this group of registers is > indicated by the MISCOFF register. Each capability has a capability ID to > determine which functionality is supported and each capability will point > to the next capability supported. > > Add a basic function to read those capabilities offsets. Sounds like an MHI version of pci_find_capability(). Maybe could be named similarly too? > Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com> > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> > --- > drivers/bus/mhi/common.h | 4 ++++ > drivers/bus/mhi/host/init.c | 29 +++++++++++++++++++++++++++++ > 2 files changed, 33 insertions(+) > > diff --git a/drivers/bus/mhi/common.h b/drivers/bus/mhi/common.h > index dda340aaed95..eedac801b800 100644 > --- a/drivers/bus/mhi/common.h > +++ b/drivers/bus/mhi/common.h > @@ -16,6 +16,7 @@ > #define MHICFG 0x10 > #define CHDBOFF 0x18 > #define ERDBOFF 0x20 > +#define MISCOFF 0x24 > #define BHIOFF 0x28 > #define BHIEOFF 0x2c > #define DEBUGOFF 0x30 > @@ -113,6 +114,9 @@ > #define MHISTATUS_MHISTATE_MASK GENMASK(15, 8) > #define MHISTATUS_SYSERR_MASK BIT(2) > #define MHISTATUS_READY_MASK BIT(0) > +#define MISC_CAP_MASK GENMASK(31, 0) > +#define CAP_CAPID_MASK GENMASK(31, 24) > +#define CAP_NEXT_CAP_MASK GENMASK(23, 12) > > /* Command Ring Element macros */ > /* No operation command */ > diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c > index a9b1f8beee7b..0b14b665ed15 100644 > --- a/drivers/bus/mhi/host/init.c > +++ b/drivers/bus/mhi/host/init.c > @@ -467,6 +467,35 @@ int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl) > return ret; > } > > +static int mhi_get_capability_offset(struct mhi_controller *mhi_cntrl, u32 capability, u32 *offset) > +{ > + u32 val, cur_cap, next_offset; > + int ret; > + > + /* get the 1st supported capability offset */ > + ret = mhi_read_reg_field(mhi_cntrl, mhi_cntrl->regs, MISCOFF, > + MISC_CAP_MASK, offset); > + if (ret) > + return ret; > + do { > + if (*offset >= mhi_cntrl->reg_len) > + return -ENXIO; > + > + ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, *offset, &val); > + if (ret) > + return ret; > + > + cur_cap = FIELD_PREP(CAP_CAPID_MASK, val); > + next_offset = FIELD_PREP(CAP_NEXT_CAP_MASK, val); > + if (cur_cap == capability) > + return 0; > + > + *offset = next_offset; > + } while (next_offset); > + > + return -ENXIO; > +} > + > int mhi_init_mmio(struct mhi_controller *mhi_cntrl) > { > u32 val; > > -- > 2.34.1 >
diff --git a/drivers/bus/mhi/common.h b/drivers/bus/mhi/common.h index dda340aaed95..eedac801b800 100644 --- a/drivers/bus/mhi/common.h +++ b/drivers/bus/mhi/common.h @@ -16,6 +16,7 @@ #define MHICFG 0x10 #define CHDBOFF 0x18 #define ERDBOFF 0x20 +#define MISCOFF 0x24 #define BHIOFF 0x28 #define BHIEOFF 0x2c #define DEBUGOFF 0x30 @@ -113,6 +114,9 @@ #define MHISTATUS_MHISTATE_MASK GENMASK(15, 8) #define MHISTATUS_SYSERR_MASK BIT(2) #define MHISTATUS_READY_MASK BIT(0) +#define MISC_CAP_MASK GENMASK(31, 0) +#define CAP_CAPID_MASK GENMASK(31, 24) +#define CAP_NEXT_CAP_MASK GENMASK(23, 12) /* Command Ring Element macros */ /* No operation command */ diff --git a/drivers/bus/mhi/host/init.c b/drivers/bus/mhi/host/init.c index a9b1f8beee7b..0b14b665ed15 100644 --- a/drivers/bus/mhi/host/init.c +++ b/drivers/bus/mhi/host/init.c @@ -467,6 +467,35 @@ int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl) return ret; } +static int mhi_get_capability_offset(struct mhi_controller *mhi_cntrl, u32 capability, u32 *offset) +{ + u32 val, cur_cap, next_offset; + int ret; + + /* get the 1st supported capability offset */ + ret = mhi_read_reg_field(mhi_cntrl, mhi_cntrl->regs, MISCOFF, + MISC_CAP_MASK, offset); + if (ret) + return ret; + do { + if (*offset >= mhi_cntrl->reg_len) + return -ENXIO; + + ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, *offset, &val); + if (ret) + return ret; + + cur_cap = FIELD_PREP(CAP_CAPID_MASK, val); + next_offset = FIELD_PREP(CAP_NEXT_CAP_MASK, val); + if (cur_cap == capability) + return 0; + + *offset = next_offset; + } while (next_offset); + + return -ENXIO; +} + int mhi_init_mmio(struct mhi_controller *mhi_cntrl) { u32 val;