@@ -1340,6 +1340,7 @@ enum {
MT_NIC_CAP_ANTSWP = 0x16,
MT_NIC_CAP_WFDMA_REALLOC,
MT_NIC_CAP_6G,
+ MT_NIC_CAP_CHIP_CAP = 0x20,
};
#define UNI_WOW_DETECT_TYPE_MAGIC BIT(0)
@@ -557,6 +557,9 @@ static int mt7921_mcu_get_nic_capability(struct mt792x_phy *mphy)
mt7921_mcu_parse_tx_resource(phy->dev,
skb);
break;
+ case MT_NIC_CAP_CHIP_CAP:
+ memcpy(&mphy->chip_cap, (void *)skb->data, sizeof(u64));
+ break;
default:
break;
}
@@ -1243,7 +1246,8 @@ int __mt7921_mcu_set_clc(struct mt792x_dev *dev, u8 *alpha2,
struct mt7921_clc *clc,
u8 idx)
{
- struct sk_buff *skb;
+#define CLC_CAP_EVT_EN BIT(0)
+ struct sk_buff *skb, *ret_skb = NULL;
struct {
u8 ver;
u8 pad0;
@@ -1251,7 +1255,7 @@ int __mt7921_mcu_set_clc(struct mt792x_dev *dev, u8 *alpha2,
u8 idx;
u8 env;
u8 acpi_conf;
- u8 pad1;
+ u8 cap;
u8 alpha2[2];
u8 type[2];
u8 env_6g;
@@ -1268,6 +1272,9 @@ int __mt7921_mcu_set_clc(struct mt792x_dev *dev, u8 *alpha2,
if (!clc)
return 0;
+ if (dev->phy.chip_cap & MT792x_CHIP_CAP_CLC_EVT_EN)
+ req.cap |= CLC_CAP_EVT_EN;
+
pos = clc->data;
for (i = 0; i < clc->nr_country; i++) {
struct mt7921_clc_rule *rule = (struct mt7921_clc_rule *)pos;
@@ -1289,10 +1296,21 @@ int __mt7921_mcu_set_clc(struct mt792x_dev *dev, u8 *alpha2,
return -ENOMEM;
skb_put_data(skb, rule->data, len);
- ret = mt76_mcu_skb_send_msg(&dev->mt76, skb,
- MCU_CE_CMD(SET_CLC), false);
+ ret = mt76_mcu_skb_send_and_get_msg(&dev->mt76, skb,
+ MCU_CE_CMD(SET_CLC),
+ !!(req.cap & CLC_CAP_EVT_EN),
+ &ret_skb);
if (ret < 0)
return ret;
+
+ if (ret_skb) {
+ struct mt7921_clc_info_tlv *info;
+
+ info = (struct mt7921_clc_info_tlv *)(ret_skb->data + 4);
+ dev->phy.clc_chan_conf = info->chan_conf;
+ dev_kfree_skb(ret_skb);
+ }
+
valid_cnt++;
}
@@ -99,4 +99,17 @@ struct mt7921_rftest_evt {
__le32 param0;
__le32 param1;
} __packed;
+
+struct mt7921_clc_info_tlv {
+ __le16 tag;
+ __le16 len;
+
+ u8 chan_conf; /* BIT(0) : Enable UNII-4
+ * BIT(1) : Enable UNII-5
+ * BIT(2) : Enable UNII-6
+ * BIT(3) : Enable UNII-7
+ * BIT(4) : Enable UNII-8
+ */
+ u8 rsv[63];
+} __packed;
#endif
@@ -27,6 +27,7 @@
#define MT7921_SDIO_HDR_PKT_TYPE GENMASK(17, 16)
#define MCU_UNI_EVENT_ROC 0x27
+#define MCU_UNI_EVENT_CLC 0x80
enum {
UNI_ROC_ACQUIRE,
@@ -25,6 +25,8 @@
#define MT792x_FW_TAG_FEATURE 4
#define MT792x_FW_CAP_CNM BIT(7)
+#define MT792x_CHIP_CAP_CLC_EVT_EN BIT(0)
+
/* NOTE: used to map mt76_rates. idx may change if firmware expands table */
#define MT792x_BASIC_RATES_TBL 11
@@ -122,6 +124,7 @@ struct mt792x_phy {
struct mt76_mib_stats mib;
u8 sta_work_count;
+ u8 clc_chan_conf;
enum mt792x_reg_power_type power_type;
struct sk_buff_head scan_event_list;
@@ -130,6 +133,7 @@ struct mt792x_phy {
void *acpisar;
#endif
void *clc[MT792x_CLC_MAX_NUM];
+ u64 chip_cap;
struct work_struct roc_work;
struct timer_list roc_timer;