@@ -51,6 +51,28 @@ mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q)
return 0;
}
+static int
+mt76_alloc_hw_queue(struct mt76_dev *dev, struct mt76_queue *q,
+ int idx, int n_desc, int bufsize,
+ u32 ring_base, u32 irq_addr,
+ u32 irq_mask)
+{
+ int ret;
+
+ q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE;
+ q->ndesc = n_desc;
+ q->buf_size = bufsize;
+ q->hw_idx = idx;
+
+ ret = mt76_dma_alloc_queue(dev, q);
+ if (ret)
+ return ret;
+
+ mt76_irq_enable(dev, irq_addr, irq_mask);
+
+ return 0;
+}
+
static int
mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q,
struct mt76_queue_buf *buf, int nbufs, u32 info,
@@ -545,7 +567,7 @@ mt76_dma_init(struct mt76_dev *dev)
static const struct mt76_queue_ops mt76_dma_ops = {
.init = mt76_dma_init,
- .alloc = mt76_dma_alloc_queue,
+ .alloc = mt76_alloc_hw_queue,
.tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw,
.tx_queue_skb = mt76_dma_tx_queue_skb,
.tx_cleanup = mt76_dma_tx_cleanup,
@@ -147,7 +147,10 @@ struct mt76_mcu_ops {
struct mt76_queue_ops {
int (*init)(struct mt76_dev *dev);
- int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q);
+ int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q,
+ int idx, int n_desc, int bufsize,
+ u32 ring_base, u32 irq_addr,
+ u32 irq_mask);
int (*add_buf)(struct mt76_dev *dev, struct mt76_queue *q,
struct mt76_queue_buf *buf, int nbufs, u32 info,
@@ -203,6 +203,24 @@ static inline void mt76x02_irq_disable(struct mt76x02_dev *dev, u32 mask)
mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
}
+static inline int
+mt76x02_init_tx_queue(struct mt76x02_dev *dev, struct mt76_queue *q,
+ int idx, int n_desc)
+{
+ return mt76_queue_alloc(dev, q, idx, n_desc, 0,
+ MT_TX_RING_BASE, MT_INT_MASK_CSR,
+ MT_INT_TX_DONE(idx));
+}
+
+static inline int
+mt76x02_init_rx_queue(struct mt76x02_dev *dev, struct mt76_queue *q,
+ int idx, int n_desc, int bufsize)
+{
+ return mt76_queue_alloc(dev, q, idx, n_desc, bufsize,
+ MT_RX_RING_BASE, MT_INT_MASK_CSR,
+ MT_INT_RX_DONE(idx));
+}
+
static inline bool
mt76x02_wait_for_txrx_idle(struct mt76_dev *dev)
{
@@ -151,44 +151,6 @@ static void mt76x02_pre_tbtt_tasklet(unsigned long arg)
spin_unlock_bh(&q->lock);
}
-static int
-mt76x02_init_tx_queue(struct mt76x02_dev *dev, struct mt76_queue *q,
- int idx, int n_desc)
-{
- int ret;
-
- q->regs = dev->mt76.mmio.regs + MT_TX_RING_BASE + idx * MT_RING_SIZE;
- q->ndesc = n_desc;
- q->hw_idx = idx;
-
- ret = mt76_queue_alloc(dev, q);
- if (ret)
- return ret;
-
- mt76x02_irq_enable(dev, MT_INT_TX_DONE(idx));
-
- return 0;
-}
-
-static int
-mt76x02_init_rx_queue(struct mt76x02_dev *dev, struct mt76_queue *q,
- int idx, int n_desc, int bufsize)
-{
- int ret;
-
- q->regs = dev->mt76.mmio.regs + MT_RX_RING_BASE + idx * MT_RING_SIZE;
- q->ndesc = n_desc;
- q->buf_size = bufsize;
-
- ret = mt76_queue_alloc(dev, q);
- if (ret)
- return ret;
-
- mt76x02_irq_enable(dev, MT_INT_RX_DONE(idx));
-
- return 0;
-}
-
static void mt76x02_process_tx_status_fifo(struct mt76x02_dev *dev)
{
struct mt76x02_tx_status stat;