diff mbox series

[v2] mt76x0: phy: fix restore phase in mt76x0_phy_recalibrate_after_assoc

Message ID f3efae19baefd102fa2f08f12982c1199ba51997.1539074999.git.lorenzo.bianconi@redhat.com (mailing list archive)
State Accepted
Delegated to: Kalle Valo
Headers show
Series [v2] mt76x0: phy: fix restore phase in mt76x0_phy_recalibrate_after_assoc | expand

Commit Message

Lorenzo Bianconi Oct. 9, 2018, 8:57 a.m. UTC
Fix restore value configured in MT_BBP(IBI, 9) register in
mt76x0_phy_recalibrate_after_assoc routine.

Fixes: 10de7a8b4ab9 ("mt76x0: phy files")
Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@redhat.com>
---
Changes since v1:
- use proper register name
---
 drivers/net/wireless/mediatek/mt76/mt76x0/phy.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

Comments

Felix Fietkau Oct. 9, 2018, 12:23 p.m. UTC | #1
On 2018-10-09 10:57, Lorenzo Bianconi wrote:
> Fix restore value configured in MT_BBP(IBI, 9) register in
> mt76x0_phy_recalibrate_after_assoc routine.
> 
> Fixes: 10de7a8b4ab9 ("mt76x0: phy files")
> Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@redhat.com>
Merged, thanks.

- Felix
diff mbox series

Patch

diff --git a/drivers/net/wireless/mediatek/mt76/mt76x0/phy.c b/drivers/net/wireless/mediatek/mt76/mt76x0/phy.c
index 99e0a91a2f99..29bc4e4623cd 100644
--- a/drivers/net/wireless/mediatek/mt76/mt76x0/phy.c
+++ b/drivers/net/wireless/mediatek/mt76/mt76x0/phy.c
@@ -733,9 +733,8 @@  void mt76x0_phy_recalibrate_after_assoc(struct mt76x02_dev *dev)
 	mt76_wr(dev, MT_TX_ALC_CFG_0, 0);
 	usleep_range(500, 700);
 
-	reg_val = mt76_rr(dev, 0x2124);
-	reg_val &= 0xffffff7e;
-	mt76_wr(dev, 0x2124, reg_val);
+	reg_val = mt76_rr(dev, MT_BBP(IBI, 9));
+	mt76_wr(dev, MT_BBP(IBI, 9), 0xffffff7e);
 
 	mt76x02_mcu_calibrate(dev, MCU_CAL_RXDCOC, 0, false);
 
@@ -746,7 +745,7 @@  void mt76x0_phy_recalibrate_after_assoc(struct mt76x02_dev *dev)
 	mt76x02_mcu_calibrate(dev, MCU_CAL_RXIQ, is_5ghz, false);
 	mt76x02_mcu_calibrate(dev, MCU_CAL_RX_GROUP_DELAY, is_5ghz, false);
 
-	mt76_wr(dev, 0x2124, reg_val);
+	mt76_wr(dev, MT_BBP(IBI, 9), reg_val);
 	mt76_wr(dev, MT_TX_ALC_CFG_0, tx_alc);
 	msleep(100);