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[0123/1094] drm/i915: Drop WaDisableTDLUnitClockGating:vlv

Message ID 1413889294-31328-124-git-send-email-dheerajx.s.jamwal@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Dheeraj Jamwal Oct. 21, 2014, 10:45 a.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

WaDisableTDLUnitClockGating is only relevant for early steppings of VLV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit a7f593c71b3a89ba2c4f25b2f3ad8b9d1e530d45)

Signed-off-by: Dheeraj Jamwal <dheerajx.s.jamwal@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c |    1 -
 1 file changed, 1 deletion(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 86b50f1..3c98e24 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4935,7 +4935,6 @@  static void valleyview_init_clock_gating(struct drm_device *dev)
 	 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
 	 */
 	I915_WRITE(GEN6_UCGCTL2,
-		   GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
 		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
 
 	/* WaDisableL3Bank2xClockGate:vlv */