From patchwork Tue Oct 21 10:52:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dheeraj Jamwal X-Patchwork-Id: 5118421 Return-Path: X-Original-To: patchwork-ltsi-dev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 82224C11AC for ; Tue, 21 Oct 2014 11:41:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 879D72010F for ; Tue, 21 Oct 2014 11:41:03 +0000 (UTC) Received: from mail.linuxfoundation.org (mail.linuxfoundation.org [140.211.169.12]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 85D4F20107 for ; Tue, 21 Oct 2014 11:41:02 +0000 (UTC) Received: from mail.linux-foundation.org (localhost [127.0.0.1]) by mail.linuxfoundation.org (Postfix) with ESMTP id C7D9D1024; Tue, 21 Oct 2014 11:07:19 +0000 (UTC) X-Original-To: ltsi-dev@lists.linuxfoundation.org Delivered-To: ltsi-dev@mail.linuxfoundation.org Received: from smtp1.linuxfoundation.org (smtp1.linux-foundation.org [172.17.192.35]) by mail.linuxfoundation.org (Postfix) with ESMTPS id 642201026 for ; Tue, 21 Oct 2014 11:07:18 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by smtp1.linuxfoundation.org (Postfix) with ESMTP id D1CC91FA0F for ; Tue, 21 Oct 2014 11:07:17 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 21 Oct 2014 04:07:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,761,1406617200"; d="scan'208";a="617796889" Received: from ubuntu-desktop.png.intel.com ([10.221.122.25]) by fmsmga002.fm.intel.com with ESMTP; 21 Oct 2014 04:07:15 -0700 From: Dheeraj Jamwal To: ltsi-dev@lists.linuxfoundation.org Date: Tue, 21 Oct 2014 18:52:04 +0800 Message-Id: <1413889294-31328-525-git-send-email-dheerajx.s.jamwal@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1413889294-31328-1-git-send-email-dheerajx.s.jamwal@intel.com> References: <1413889294-31328-1-git-send-email-dheerajx.s.jamwal@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org Subject: [LTSI-dev] [PATCH 0524/1094] Revert "drm/i915: Disable/Enable PM Intrrupts based on the current freq." X-BeenThere: ltsi-dev@lists.linuxfoundation.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: "A list to discuss patches, development, and other things related to the LTSI project" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: ltsi-dev-bounces@lists.linuxfoundation.org Errors-To: ltsi-dev-bounces@lists.linuxfoundation.org X-Virus-Scanned: ClamAV using ClamSMTP From: Chris Wilson This reverts commit 2754436913b94626a5414d82f0996489628c513d. Conflicts: drivers/gpu/drm/i915/i915_irq.c The partial application of interrupt masking without regard to other pathways for adjusting the RPS frequency results in completely disabling the PM interrupts. This leads to excessive power consumption as the GPU is kept at max clocks (until the failsafe mechanism fires of explicitly downclocking the GPU when all requests are idle). Or equally as bad for the UX, the GPU is kept at minimum clocks and prevented from upclocking in response to a requirement for more power. Testcase: pm_rps/blocking Cc: Deepak S Cc: Ville Syrjälä Cc: Daniel Vetter Signed-off-by: Chris Wilson Reviewed-by:Deepak S Signed-off-by: Daniel Vetter (cherry picked from commit 037bde19a43e299d30f0490bba9be32ab355975c) Signed-off-by: Dheeraj Jamwal --- drivers/gpu/drm/i915/i915_drv.h | 3 --- drivers/gpu/drm/i915/i915_irq.c | 38 -------------------------------------- drivers/gpu/drm/i915/intel_pm.c | 8 -------- 3 files changed, 49 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 537404b..8d10f22 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1001,9 +1001,6 @@ struct intel_gen6_power_mgmt { u8 rp1_freq; /* "less than" RP0 power/freqency */ u8 rp0_freq; /* Non-overclocked max frequency. */ - bool rp_up_masked; - bool rp_down_masked; - int last_adj; enum { LOW_POWER, BETWEEN, HIGH_POWER } power; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index d1baf66..e88452f 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1084,43 +1084,6 @@ static void notify_ring(struct drm_device *dev, i915_queue_hangcheck(dev); } -void gen6_set_pm_mask(struct drm_i915_private *dev_priv, - u32 pm_iir, int new_delay) -{ - if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { - if (new_delay >= dev_priv->rps.max_freq_softlimit) { - /* Mask UP THRESHOLD Interrupts */ - I915_WRITE(GEN6_PMINTRMSK, - I915_READ(GEN6_PMINTRMSK) | - GEN6_PM_RP_UP_THRESHOLD); - dev_priv->rps.rp_up_masked = true; - } - if (dev_priv->rps.rp_down_masked) { - /* UnMask DOWN THRESHOLD Interrupts */ - I915_WRITE(GEN6_PMINTRMSK, - I915_READ(GEN6_PMINTRMSK) & - ~GEN6_PM_RP_DOWN_THRESHOLD); - dev_priv->rps.rp_down_masked = false; - } - } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { - if (new_delay <= dev_priv->rps.min_freq_softlimit) { - /* Mask DOWN THRESHOLD Interrupts */ - I915_WRITE(GEN6_PMINTRMSK, - I915_READ(GEN6_PMINTRMSK) | - GEN6_PM_RP_DOWN_THRESHOLD); - dev_priv->rps.rp_down_masked = true; - } - - if (dev_priv->rps.rp_up_masked) { - /* UnMask UP THRESHOLD Interrupts */ - I915_WRITE(GEN6_PMINTRMSK, - I915_READ(GEN6_PMINTRMSK) & - ~GEN6_PM_RP_UP_THRESHOLD); - dev_priv->rps.rp_up_masked = false; - } - } -} - static void gen6_pm_rps_work(struct work_struct *work) { drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, @@ -1180,7 +1143,6 @@ static void gen6_pm_rps_work(struct work_struct *work) dev_priv->rps.min_freq_softlimit, dev_priv->rps.max_freq_softlimit); - gen6_set_pm_mask(dev_priv, pm_iir, new_delay); dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; if (IS_VALLEYVIEW(dev_priv->dev)) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 87084fc..f965ddc 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3095,11 +3095,6 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, I915_READ(VLV_GTLC_SURVIVABILITY_REG) & ~VLV_GFX_CLK_FORCE_ON_BIT); - - /* Unmask Up interrupts */ - dev_priv->rps.rp_up_masked = true; - gen6_set_pm_mask(dev_priv, GEN6_PM_RP_DOWN_THRESHOLD, - dev_priv->rps.min_freq_softlimit); } void gen6_rps_idle(struct drm_i915_private *dev_priv) @@ -3688,9 +3683,6 @@ static void valleyview_enable_rps(struct drm_device *dev) valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); - dev_priv->rps.rp_up_masked = false; - dev_priv->rps.rp_down_masked = false; - gen6_enable_rps_interrupts(dev); gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);