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[0942/1094] drm/i915/chv: Implement WaDisableCSUnitClockGating:chv

Message ID 1413889294-31328-943-git-send-email-dheerajx.s.jamwal@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Dheeraj Jamwal Oct. 21, 2014, 10:59 a.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This workaround is listed for CHV, but not for BDW. However BSpec notes
that on BDW CSunit clock gating is always disabled irrespective of the
relevant bit in the GEN6_UGCTL1 registers. For CHV however, such text
is not present in BSpec, so it seems safer to just set the bit.

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit 0846697c6710a83bdacfe92b92c03288d87e24d9)

Signed-off-by: Dheeraj Jamwal <dheerajx.s.jamwal@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c |    4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8e90771..258d397 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5433,6 +5433,10 @@  static void cherryview_init_clock_gating(struct drm_device *dev)
 	/* WaDisableSemaphoreAndSyncFlipWait:chv */
 	I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
 		   _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
+
+	/* WaDisableCSUnitClockGating:chv */
+	I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
+		   GEN6_CSUNIT_CLOCK_GATE_DISABLE);
 }
 
 static void g4x_init_clock_gating(struct drm_device *dev)