[net,0/1] net: fec: Fix RMII clock glitch in FEC

Message

Badel, Laurent Jan. 22, 2021, 3:13 p.m. UTC

The FEC drivers performs a "hardware reset" of the MAC module when the
link is reported to be up. This causes a short glitch in the RMII clock 
due to the hardware reset clearing the receive control register which 
controls the MII mode. It seems that some link partners do not tolerate 
this glitch, and invalidate the link, which leads to a never-ending loop
of negotiation-link up-link down events. 

This was observed with the iMX28 Soc and LAN8720/LAN8742 PHYs, with two 
Intel adapters I218-LM and X722-DA2 as link partners, though a number of
other link partners do not seem to mind the clock glitch. Changing the 
hardware reset to a software reset (clearing bit 1 of the ECR register) 
cured the issue.

Attempts to optimize fec_restart() in order to minimize the duration of 
the glitch were unsuccessful. Furthermore manually producing the glitch by
setting MII mode and then back to RMII in two consecutive instructions, 
resulting in a clock glitch <10us in duration, was enough to cause the 
partner to invalidate the link. This strongly suggests that the root cause
of the link being dropped is indeed the change in clock frequency.

In an effort to minimize changes to driver, the patch proposes to use 
soft reset only for tested SoCs (iMX28) and only if the link is up. This 
preserves hardware reset in other situations, which might be required for
proper setup of the MAC.  

Laurent Badel (1):
  Fix temporary RMII clock reset on link up

 drivers/net/ethernet/freescale/fec.h      | 5 +++++
 drivers/net/ethernet/freescale/fec_main.c | 6 ++++--
 2 files changed, 9 insertions(+), 2 deletions(-)