From patchwork Mon Jul 19 14:38:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 12385993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D5E7C07E9D for ; Mon, 19 Jul 2021 14:39:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0FD8E610FB for ; Mon, 19 Jul 2021 14:39:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241159AbhGSN7H (ORCPT ); Mon, 19 Jul 2021 09:59:07 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:4499 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S232395AbhGSN7F (ORCPT ); Mon, 19 Jul 2021 09:59:05 -0400 X-IronPort-AV: E=Sophos;i="5.84,252,1620658800"; d="scan'208";a="88086566" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 19 Jul 2021 23:39:43 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 0C4694003EC3; Mon, 19 Jul 2021 23:39:39 +0900 (JST) From: Lad Prabhakar To: Geert Uytterhoeven , Rob Herring , Fabrizio Castro , Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Jakub Kicinski , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 0/5] Renesas RZ/G2L CANFD support Date: Mon, 19 Jul 2021 15:38:06 +0100 Message-Id: <20210719143811.2135-1-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Hi All, This patch series adds CANFD support to Renesas RZ/G2L family. CANFD block on RZ/G2L SoC is almost identical to one found on R-Car Gen3 SoC's. On RZ/G2L SoC interrupt sources for each channel are split into individual sources. Cheers, Prabhakar Changes for v2: * Added interrupt-names property and marked it as required for RZ/G2L family * Added descriptions for reset property * Re-used irq handlers on RZ/G2L SoC * Added new enum for chip_id * Dropped R9A07G044_LAST_CORE_CLK * Dropped patch (clk: renesas: r9a07g044-cpg: Add clock and reset entries for CANFD) as its been merged into renesas tree Lad Prabhakar (5): dt-bindings: net: can: renesas,rcar-canfd: Document RZ/G2L SoC can: rcar_canfd: Add support for RZ/G2L family dt-bindings: clk: r9a07g044-cpg: Add entry for P0_DIV2 core clock clk: renesas: r9a07g044-cpg: Add entry for fixed clock P0_DIV2 arm64: dts: renesas: r9a07g044: Add CANFD node .../bindings/net/can/renesas,rcar-canfd.yaml | 66 ++++++- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 42 +++++ drivers/clk/renesas/r9a07g044-cpg.c | 3 +- drivers/net/can/rcar/rcar_canfd.c | 178 +++++++++++++++--- include/dt-bindings/clock/r9a07g044-cpg.h | 1 + 5 files changed, 252 insertions(+), 38 deletions(-) base-commit: 2734d6c1b1a089fb593ef6a23d4b70903526fe0c