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Thu, 24 Mar 2022 03:40:12 +0000 From: "Peng Fan (OSS)" To: ulf.hansson@linaro.org, robh+dt@kernel.org, krzk+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, wg@grandegger.com, mkl@pengutronix.de, davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com, qiangqing.zhang@nxp.com Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-can@vger.kernel.org, netdev@vger.kernel.org, Peng Fan Subject: [PATCH 0/4] dt-bindings: imx: add nvmem property Date: Thu, 24 Mar 2022 12:20:20 +0800 Message-Id: <20220324042024.26813-1-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.35.1 X-ClientProxiedBy: SG2PR01CA0172.apcprd01.prod.exchangelabs.com (2603:1096:4:28::28) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8f13699b-0f84-4915-577b-08da0d480026 X-MS-TrafficTypeDiagnostic: DBAPR04MB7223:EE_ X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xUXERlizuBTqJyGjurUVka52Ywqqh5Mueyaq5dh+kcYtdUybqOWvbSzmtaWE43dPcuhmId9NTZBzaeABy6Zcpbr0MVJEDolh6ylVt4GNT8xRtd7CP85fQp2YmxCVlgi5Wc+xA9FIEff7vfFJ7f/iSPDWrfOkHHUYl1Lq3kYWR6iqUh23LzJQxZUJ5jwnzjwHPszz2Rz4Y+l08N36VHRNKYWbN17ui0Ncz68sk3eQ74YiqiYrukPAHzHI3+EGeTqrDQ0k1GDksVHyk0CiXgh4o5EDKv2i6Dio4+8CRy4QqS7txuqEk0Qu2BQlkM1Q23FWYS4i4KiUB/RdLl5/6b5YGlUVOXfttYNAEBpUFW3bv2dYjyvQECWd+lnTaoTIIWA4K9wdcApmXi9HoJPiypfAxavrZiXr58gD7Cief1LuUY9eLX/Y435hZwJ3dgdOL/XdCjTOvw9AqkKuX43GE+cNTSDVlt6b0bM02UxxlgEnRVBM390nUrVwac1++7ofRSSuxvaINllQwNEQUqp/nh2QKqkrlExfUqJyVrUQI0gyvJCaQ6uD3LlVwuadoQX3km4J9cvz2Rk8d5d4hBwFpGMoqkTbLWZ6Qi9k4JAdz81L7Uwwzn5P061L/ZP424SwxXlq+8QGN6Aqz//TYCsPEI8WyB7yYd551hT4JAhO0+wP76gpoWEtCgcKJasOih3GK5WlBPQ1OrGHk9jotzGvK8u5c5cULtmwzf0El06AOLHRNiwWW9Li81lvAdEtn2u48+b4iHybeVW6tjUh4LOW6n9/Lpq4egxChIt3nqBZLGzVufa4vaU7c/PyXhS0JNxGdN9ZBSspBIrBW712FKatAKl5eOLqSqgraS9SN1Yu0EsJxFbPLA2g+SB3emAlxGsXlJP5O1O9xs1iGoTm3dXESUD3AlknhfKine/+n6vNdZUwOy38mH9MM9ARonGSpRsg5rpYkVtPEAmHvb2GcgV7DhoDl58P8MTmfu4jJo9XBXEmZ1yxI8Uk0vcTLrBgWDCMcKsEIwcCxiVl72JloX8n/lEVqev0QdBbSLbHKMSMY7q8ix5fZdNXdQ9cSfcGIFHNWbsW96H2o3C/zprNCD4yLIv/dOomANoxDF7td+5wFsCAdSNiKu7Qu1BKuAuuk9oUkX2rljVYiCTiU5tbrzmPbCbGqvB4YEaqaSPP+bDj9RvDamaOkf0Z0b3ODWes4/x+sYk++twCGv4SsAb5UnFz0BrghnqxrPurayj7/K/nhvmJcNR9qkum9p/XB93PjT5UFiIWbNFddMFgcdt6KJtBhJ2dpJek61XRsXbngJBqn9YZa4/kvZpounSsO8CHs9pBNqlt3yYDaYOgpZ/X60C61SgbEJTgUeEzcB+G87uXWUxIlvFt/IhzwZ/fNRNrspSnvb2BxsWGVrHY7YsHrIsm4GS/1JahiGbnCiQl+OCXFuOFepz4VIO4lSu+IkP8pMVubIbtwVr74bjPUeJ/h2fwrrvZ9L9kLlFUuhOyntzNvCiPJCzp9gwJukRxk7Uf1pjdCyC9EVtVkX/LiiwECSV2vG0hNvTKxjPwi/4LQRXUyAa/d6Baob5uAHprw5BaiuY2ZR/2przHA3f7sVEqYmTxLprimD7l/qgkhVSeqOzP2ZbiFelH6MiNflq61p458Knx2pP8WlrQcy2kufqIHQfHEQeUfi/Lk/3EadWzMN75fwZ2fAMWgx+opvPt30yknGG9OvtBCzAqSsjMYknonMMFQJSVVw== X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8f13699b-0f84-4915-577b-08da0d480026 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2022 03:40:12.0790 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LV7N4iIQ38fkDGOyOvVwAUXkgH5T/K6pLYjZkRaacHFxzEKeLrQtDGyA2fyJMPlPwteHBVqLX6KUi1N7m1JhYA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7223 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Peng Fan To i.MX SoC, there are many variants, such as i.MX8M Plus which feature 4 A53, GPU, VPU, SDHC, FLEXCAN, FEC, eQOS and etc. But i.MX8M Plus has many parts, one part may not have FLEXCAN, the other part may not have eQOS or GPU. But we use one device tree to support i.MX8MP including its parts, then we need update device tree to mark the disabled IP status "disabled". In NXP U-Boot, we hardcoded node path and runtime update device tree status in U-Boot according to fuse value. But this method is not scalable and need encoding all the node paths that needs check. By introducing nvmem property for each node that needs runtime update status property accoridng fuse value, we could use one Bootloader code piece to support all i.MX SoCs. The drawback is we need nvmem property for all the nodes which maybe fused out. Rob: I only include limited node bindings in this patchset, and not include device tree patch. Just wanna to see whether you agree this approach. If you agree, I'll later post device tree part and other dt-bindings update, such as MU, USB and etc. Thanks. Example as below: flexcan1: can@308c0000 { .... nvmem-cells = <&flexcan_disabled>; nvmem-cell-names = "disabled"; }; flexcan2: can@308d0000 { .... nvmem-cells = <&flexcan_disabled>; nvmem-cell-names = "disabled"; }; ocotp: efuse@30350000 { compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; /* For nvmem subnodes */ #address-cells = <1>; #size-cells = <1>; m7_disabled: m7@10 { reg = <0x10 4>; bits = <21 1>; }; g1_disabled: g1@10 { reg = <0x10 4>; bits = <24 1>; }; g2_disabled: g2@10 { reg = <0x10 4>; bits = <25 1>; }; can_disabled: can@10 { reg = <0x10 4>; bits = <28 1>; }; canfd_disabled: canfd@10 { reg = <0x10 4>; bits = <29 1>; }; vc8000e_disabled: vc8000e@10 { reg = <0x10 4>; bits = <30 1>; }; isp1_disabled: isp1@10 { reg = <0x14 4>; bits = <0 1>; }; isp2_disabled: isp2@10 { reg = <0x14 4>; bits = <1 1>; }; dewrap_disabled: dewrap@10 { reg = <0x14 4>; bits = <2 1>; }; npu_disabled: dewrap@10 { reg = <0x14 4>; bits = <3 1>; }; dsp_disabled: dewrap@10 { reg = <0x14 4>; bits = <4 1>; }; asrc_disabled: dewrap@10 { reg = <0x14 4>; bits = <5 1>; }; gpu2d_disabled: gpu2d@10 { reg = <0x14 4>; bits = <6 1>; }; gpu3d_disabled: gpu3d@10 { reg = <0x14 4>; bits = <7 1>; }; usb1_disabled: usb1@10 { reg = <0x14 4>; bits = <8 1>; }; usb2_disabled: usb2@10 { reg = <0x14 4>; bits = <9 1>; }; pcie1_disabled: pcie1@10 { reg = <0x14 4>; bits = <11 1>; }; enet1_disabled: enet1@10 { reg = <0x14 4>; bits = <13 1>; }; enet2_disabled: enet2@10 { reg = <0x14 4>; bits = <14 1>; }; csi1_disabled: csi1@10 { reg = <0x14 4>; bits = <15 1>; }; csi2_disabled: csi1@10 { reg = <0x14 4>; bits = <16 1>; }; dsi1_disabled: dsi1@10 { reg = <0x14 4>; bits = <17 1>; }; lvds1_disabled: lvds1@10 { reg = <0x14 4>; bits = <19 1>; }; lvds2_disabled: lvds1@10 { reg = <0x14 4>; bits = <19 1>; }; eth_mac1: mac-address@90 { reg = <0x90 6>; }; eth_mac2: mac-address@96 { reg = <0x96 6>; }; }; Peng Fan (4): dt-bindings: can: fsl,flexcan: introduce nvmem property dt-bindings: net: fsl,fec: introduce nvmem property dt-bindings: mmc: imx-esdhc: introduce nvmem property dt-bindings: net: imx-dwmac: introduce nvmem property Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 9 +++++++++ .../devicetree/bindings/net/can/fsl,flexcan.yaml | 9 +++++++++ Documentation/devicetree/bindings/net/fsl,fec.yaml | 9 +++++++++ Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml | 9 +++++++++ 4 files changed, 36 insertions(+)