From patchwork Mon May 15 19:03:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Piotr Raczynski X-Patchwork-Id: 13242072 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4823018C21 for ; Mon, 15 May 2023 19:03:30 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD55511A for ; Mon, 15 May 2023 12:03:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684177405; x=1715713405; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=vT7CYSKsAkJfckRs6Q+2GoeK9sPvoI1a2zZKXSAvc6Y=; b=Gs7UfDHgiEbYZA3LkmDBpBOvklf4a659udj1TsDmZV47dh6pxHShpfOJ sRXgYYGXHXstAaFmDnw+4VSe4izosLAA2Giwfe1e9e9w3ou1bEYkPQDMy xymlSmETXawodT0gjYA3Yxer2zSbqXdCqaMrgXMeiPxue43+8azcJOVQv FJK/loMjyp0v5wiDYYOkiY7z6KK0ZpzaE/a9+Z5VJSvUw8mwK3zEZK2oT SaUcvPGryPn4z7F5ynvAc5cx91/amASpz05IL23Q+Qa7dX2COAE5PpGh1 0PcKf0QBMh9urhKu9LXCXWw6rTVXp9iDyw+pdgxobAy5OOmzCRHHghpec A==; X-IronPort-AV: E=McAfee;i="6600,9927,10711"; a="354450555" X-IronPort-AV: E=Sophos;i="5.99,277,1677571200"; d="scan'208";a="354450555" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 May 2023 12:03:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10711"; a="766074863" X-IronPort-AV: E=Sophos;i="5.99,277,1677571200"; d="scan'208";a="766074863" Received: from nimitz.igk.intel.com ([10.102.21.231]) by fmsmga008.fm.intel.com with ESMTP; 15 May 2023 12:03:22 -0700 From: Piotr Raczynski To: intel-wired-lan@osuosl.org Cc: netdev@vger.kernel.org, michal.swiatkowski@intel.com, shiraz.saleem@intel.com, jacob.e.keller@intel.com, sridhar.samudrala@intel.com, jesse.brandeburg@intel.com, aleksander.lobakin@intel.com, lukasz.czapnik@intel.com, simon.horman@corigine.com, Piotr Raczynski Subject: [PATCH iwl-next v5 0/8] ice: support dynamic interrupt allocation Date: Mon, 15 May 2023 21:03:11 +0200 Message-Id: <20230515190319.808985-1-piotr.raczynski@intel.com> X-Mailer: git-send-email 2.38.1 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net This patchset reimplements MSIX interrupt allocation logic to allow dynamic interrupt allocation after MSIX has been initially enabled. This allows current and future features to allocate and free interrupts as needed and will help to drastically decrease number of initially preallocated interrupts (even down to the API hard limit of 1). Although this patchset does not change behavior in terms of actual number of allocated interrupts during probe, it will be subject to change. First few patches prepares to introduce dynamic allocation by moving interrupt allocation code to separate file and update allocation API used in the driver to the currently preferred one. Due to the current contract between ice and irdma driver which is directly accessing msix entries allocated by ice driver, even after moving away from older pci_enable_msix_range function, still keep msix_entries array for irdma use. Next patches refactors and removes redundant code from SRIOV related logic as it also make it easier to move away from static allocation scheme. Last patches actually enables dynamic allocation of MSIX interrupts. First, introduce functions to allocate and free interrupts individually. This sets ground for the rest of the changes even if that patch still allocates the interrupts from the preallocated pool. Since this patch starts to keep interrupt details in ice_q_vector structure we can get rid of functions that calculates base vector number and register offset for the interrupt as it is equal to the interrupt index. Only keep separate register offset functions for the VF VSIs. Next, replace homegrown interrupt tracker with much simpler xarray based approach. As new API always allocate interrupts one by one, also track interrupts in the same manner. Lastly, extend the interrupt tracker to deal both with preallocated and dynamically allocated vectors and use pci_msix_alloc_irq_at and pci_msix_free_irq functions. Since not all architecture supports dynamic allocation, check it before trying to allocate a new interrupt. As previously mentioned, this patchset does not change number of initially allocated interrupts during init phase but now it can and will likely be changed. Patch 1-3 -> move code around and use newer API Patch 4-5 -> refactor and remove redundant SRIOV code Patch 6 -> allocate every interrupt individually Patch 7 -> replace homegrown interrupt tracker with xarray Patch 8 -> allow dynamic interrupt allocation Change history: v1 -> v2: - ice: refactor VF control VSI interrupt handling - move ice_get_vf_ctrl_vsi to ice_lib.c (ice_vf_lib.c depends on CONFIG_PCI_IOV) v2 -> v3: - ice: refactor VF control VSI interrupt handling - revert v2 change and add no-op function in case of CONFIG_PCI_IOV=n - ice: add dynamic interrupt allocation - fix commit message v3 -> v4: - ice: add individual interrupt allocation - don't use devm alloc/free for q_vectors - ice: track interrupt vectors with xarray - just return NULL instead of goto if interrupt allocation failed - ice: add dynamic interrupt allocation - exit if released irq entry was not found in the tracker v4 -> v5: - ice: add dynamic interrupt allocation - prevent q_vector leak in case vf ctrl VSI error - ice: refactor VF control VSI interrupt handling - simplify ice_vsi_setup_vector_base and account for num_avail_sw_msix Piotr Raczynski (8): ice: move interrupt related code to separate file ice: use pci_irq_vector helper function ice: use preferred MSIX allocation api ice: refactor VF control VSI interrupt handling ice: remove redundant SRIOV code ice: add individual interrupt allocation ice: track interrupt vectors with xarray ice: add dynamic interrupt allocation drivers/net/ethernet/intel/ice/Makefile | 1 + drivers/net/ethernet/intel/ice/ice.h | 24 +- drivers/net/ethernet/intel/ice/ice_arfs.c | 5 +- drivers/net/ethernet/intel/ice/ice_base.c | 50 ++- drivers/net/ethernet/intel/ice/ice_ethtool.c | 2 +- drivers/net/ethernet/intel/ice/ice_idc.c | 54 ++- drivers/net/ethernet/intel/ice/ice_irq.c | 378 +++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_irq.h | 25 ++ drivers/net/ethernet/intel/ice/ice_lib.c | 288 +------------- drivers/net/ethernet/intel/ice/ice_lib.h | 5 - drivers/net/ethernet/intel/ice/ice_main.c | 268 ++----------- drivers/net/ethernet/intel/ice/ice_ptp.c | 2 +- drivers/net/ethernet/intel/ice/ice_sriov.c | 43 +-- drivers/net/ethernet/intel/ice/ice_vf_lib.c | 32 ++ drivers/net/ethernet/intel/ice/ice_vf_lib.h | 7 + drivers/net/ethernet/intel/ice/ice_xsk.c | 5 +- 16 files changed, 569 insertions(+), 620 deletions(-) create mode 100644 drivers/net/ethernet/intel/ice/ice_irq.c create mode 100644 drivers/net/ethernet/intel/ice/ice_irq.h