From patchwork Thu Aug 17 16:57:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13356822 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB3FA33D1 for ; Thu, 17 Aug 2023 17:09:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 59D18C433C8; Thu, 17 Aug 2023 17:09:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1692292174; bh=/IF04sHkLLuYwZg5UDGG+9COl2K4c5dV5hCvL3rgYGo=; h=From:To:Cc:Subject:Date:From; b=jGCwjPthnd6uH4tJfKVWBnQmxaCK2g/kXtyb2msrBxtoW25nEs7w1Ajj/BW+fpY6p ItcloqGHp1tbzAHwf4QfunNDFPfY7UB2kiKfKvAkHdYjt+pHMEWCAnaS9nmhH+m+UE AvW4HFjtvK0lKfL35Mniy6hFbixtI9oMmTXRTqaUQsroGbbvE5Vhk2KHNcvv9WZ3Jt Zat6t4/CaGZykYor1fD6Jm7h7kGHsLKEVbAKRIQ7xc53TTEnl0O1eJmmcwZG3T2Jkn zbIErRgMecOnIu7Y45iR/vX7Ke8LrJy7n9fHjsa9uoqKp6DBsRnKQG69QAWu9GDFOl nPipyytJQzJJQ== From: Jisheng Zhang To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Subject: [PATCH net-next v5 0/9] net: stmmac: add new features to xgmac Date: Fri, 18 Aug 2023 00:57:40 +0800 Message-Id: <20230817165749.672-1-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org This series add below new features to xgmac: correct RX COE parsing add more feature parsing from hw cap enlarge C22 ADDR and rx/tx channels support parse safety ce/ue irq from DT support per channel irq Since v4: - move "additionalItems" and "maxItems" a bit earlier to patch5 to fix "interrupt-names... is too long" Since v3: - collect Acked-by tag - remove patch which enlarges the max XGMAC C22 ADDR to 31 since it's merged - s/stmmac_request_irq_multi/stmmac_request_irq_multi_channel - update the dt-binding to refelct the optional per-channel irq: - use enum - add additionalItems and maxItems to fix the "interrupt-names .. is too long" Since v2: - check per channel irq by (res->rx_irq[0] > 0 && res->tx_irq[0] > 0) rather than (res->rx_irq[0] && res->tx_irq[0]) - bypass if (irq <= 0) when request rx/tx irq Since v1: - remove "_irq" suffix from safety irqs dt binding - remove "snps,per-channel-interrupt" dt binding, check the channel irq instead. - more renaming about "msi" to reflect per channel irq isn't MSI specific Jisheng Zhang (9): net: stmmac: correct RX COE parsing for xgmac net: stmmac: xgmac: add more feature parsing from hw cap net: stmmac: enlarge max rx/tx queues and channels to 16 net: stmmac: reflect multi irqs for tx/rx channels and mac and safety net: stmmac: xgmac: support per-channel irq dt-bindings: net: snps,dwmac: add safety irq support net: stmmac: platform: support parsing safety irqs from DT dt-bindings: net: snps,dwmac: add per channel irq support net: stmmac: platform: support parsing per channel irq from DT .../devicetree/bindings/net/snps,dwmac.yaml | 77 ++++++++++++++++++- .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 4 +- .../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 2 +- .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 + .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 5 +- .../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 34 ++++---- .../net/ethernet/stmicro/stmmac/stmmac_main.c | 56 +++++++------- .../ethernet/stmicro/stmmac/stmmac_platform.c | 35 +++++++++ include/linux/stmmac.h | 10 +-- 9 files changed, 172 insertions(+), 53 deletions(-)